Network-on-Chip Research Articles

Integrated WDM-compatible optical mode division multiplexing neural network accelerator

On-chip photonic neural networks (PNN) are emerging as an attractive solution for artificial neural networks due to their high computing density, low energy consumption, and compact size. Matrix-vector multiplication (MVM) plays a key role in on-chip PNN, and can achieve high-speed multiply-accumulate operation. Most current schemes implement MVM by adopting wavelength division multiplexing technology to accumulate the power of different wavelengths together. This requires multiple laser sources. Additionally, both positive and negative domain MVM are inevitable for realizing precise PNNs, but because of the innate limitations of light, effective solutions to perform negative value computing are still inadequate. Here, we propose and demonstrate a PNN accelerator based on mode division multiplexing technology to reduce the use of multi-wavelength lasers. We show that it can satisfactorily tackle real-number-field computing (including positive and negative domains) based on a novel, to our knowledge, transformation mapping approach. As a proof-of-concept, we demonstrate a fabricated accelerator for image convolution and letter pattern detection, achieving a computing density of 1.37TOPS/mm2 under the 22.38 Gbaud modulation rate.

Circuit implementation of on-chip trainable spiking neural network using CMOS based memristive STDP synapses and LIF neurons

Computation on a large volume of data at high speed and low power requires energy-efficient architectures for edge computing applications. As a result, scientists focus on memristive circuits and systems for area and energy efficiency. Spiking neural network (SNN) with bio-inspired spike-timing-dependent plasticity learning (STDP) is a promising solution for energy-efficient neuromorphic systems than conventional artificial neural network (ANN). Previous works on SNN with STDP learning primarily use memristor macro models, which are software-based and cannot give complete insight into circuit implementation challenges. Some reported works on SNN use memristive devices, which require additional fabrication steps. This article presents a full circuit-level implementation of the SNN system featuring on-chip training and classification using memristive STDP synapse in standard CMOS technology. A new learning rule using the modified STDP is implemented to simplify the weight modification process. It does not involve FPGAs, CPUs, or GPUs to train the neural network. The approach used in this paper to modify the weights does not require any additional combinational or digital circuits attached to the memristive synapse resulting in less consumption of area, energy and time. We demonstrated the complete circuit-level design, implementation and simulation of SNN with on-chip training and pattern classification using 180 nm CMOS technology. A comprehensive comparison of the proposed SNN circuit with the previous related work is also presented. To demonstrate the versatility of the CMOS synapse circuit for application scenarios requiring rate-based learning, we have tuned the pair-based STDP circuit to obtain Bienenstock–Cooper–Munro (BCM) characteristics and applied it to heart rate classification.

Defense Against On-Chip Trojans Enabling Traffic Analysis Attacks Based on Machine Learning and Data Augmentation

Modern computing systems involve huge data exchange across various sections of the processing system. To facilitate this, Network-on-Chip (NoC) serve as a crucial infrastructure that connect the processing cores to memory, peripherals, etc. The system could be put at great risk should the NoC system become compromised. The NoCs are used in multi/many-core processors; this domain is experiencing increased threats because of Hardware Trojan (HT) embedded in the multi core processing systems due to the presence of third-party entities in the system-on-chip (SoC) design pipeline. Protecting user and system level privacy becomes important in such multi core systems to enable trust. By embedding a hardware Trojan (HT) in a NoC, the adversary can snoop on important insights regarding the applications executing on the system or the user profile information. An attack of such calibre can compromise privacy thereby enabling more advanced attack on the entire system. This work demonstrates the capability of a traffic analysis attack when a few HTs are embedded in the NoC switches of a multi/many-core processor. The attack is capable of exposing sensitive information to an external malicious attacker who can then analyze the payload data with sophisticated machine learning (ML) techniques to infer the applications executing on the system. We also evaluate the performance of a generative adversarial network (GAN) strengthened attacker model that offers more robustness for data paucity scenarios. We propose a Simulated Annealing-based randomized routing algorithm based defense for NoCs thus thwarting the attack. The results demonstrate that the proposed randomized routing algorithm could reduce the accuracy of identifying user profiles by the attacker from >98% to <15% in multi/many-core systems.

DEMAP: differential evolution mapping for network on chip optimization

Network-on-chip (NoC) is a new paradigm for system-on-chip (SoC) design, which facilitates the interconnection and integration of complex components. Since this technology is still new, significant research efforts are needed to accelerate and simplify the design phases. Mapping is a critical phase in the NoC design process, as a mismatch of application software components can significantly impact the final system's performance. Therefore, it is essential to develop automated tools and methods to ensure this step. The main objective of this project is to develop a new approach that can be used to map applications on the NoC architecture to reduce communication costs. To achieve this goal, we have opted for an optimization algorithm, specifically the differential evolution algorithm.

2D router chip design, analysis, and simulation for effective communication

&lt;p class="Correspondencedetails"&gt;&lt;span lang="EN-US"&gt;The router is a network device that is used to connect subnetwork and packet-switched networking by directing the data packets to the intended IP addresses. It succeeds the traffic between different systems and allows several devices to share the internet connection. The router is applicable for the effective commutation in system on chip (SoC) modules for network on chip (NoC) communication. The research paper emphasizes the design of the two dimensional (2D) router hardware chip in the Xilinx integrated system environment (ISE) 14.7 software and further logic verification using the data packets transmitted from all input/output ports. The design evaluation is done based on the pre-synthesis device utilization summary relating to different field programmable gate array (FPGA) boards such as Spartan-3E (XC3S500E), Spartan-6 (XC6SLX45), Virtex-4 (XC4VFX12), Virtex-5 (XC5VSX50T), and Virtex-7 (XC7VX550T). The 64-bit data logic is verified on the different ports of the router configuration in the Xilinx and Modelsim waveform simulator. The Virtex-7 has proven the fast-switching speed and optimal hardware parameters in comparison to other FPGAs.&lt;/span&gt;&lt;/p&gt;

Design of a Passive Silicon-on-Insulator-Based On-Chip Optical Circulating Network Supporting Mode Conversion and High Optical Isolation

Over the past few decades, on-chip photonic integrated circuits based on silicon photonics (SiPh) platforms have gained widespread attention due to the fact that they offer many advantages, such as high bandwidth, low loss, compact size, low power consumption, and high integration with different photonic devices. The demand for high-speed and high-performance SiPh devices is driven by the significant increase in demand for Internet traffic. In photonic integrated circuits, controlling optical signals to make them circulate in a specific direction is a highly researched area of study. However, achieving a purely passive on-chip optical circulating network on a SiPh platform is very challenging. Therefore, we propose and demonstrate, through simulations, an on-chip optical circulator network on a silicon-on-insulator (SOI) platform. The proposed device can also support mode conversion. The proposed on-chip optical circulating network consists of two kinds of tailor-made multi-mode interferometer (MMI) structures and waveguide crossings. Through the optical power division and mode combination capabilities of the MMI, an optical circulating network supporting high optical isolation and mode conversion is achieved. The proposed optical circulating network has a loss of 1.5 dB at each output port, while maintaining a high isolation of 35 dB in the transmission window from 1530 nm to 1570 nm.

Optimizing Network-on-Chip using metaheuristic algorithms: A comprehensive survey

Network on Chip (NoC) is an interesting technology that benefits from several processing elements and the necessary communication facilities, to provide an answer to the ever-growing need for more processing power. Metaheuristic algorithms are important tools that have been used for dealing with various NP-hard problems in different domains. Such algorithms are also widely used in the NoC context by many frameworks for optimizing various characteristics of the NoC environments. Nonetheless, there is a lack of a comprehensive survey to put forward a thorough study of such schemes. To fill this gap, this article presents a comprehensive survey and classification of the metaheuristic-based schemes designed for various NoC topologies. For this purpose, first, some background knowledge is provided which helps to understand the studied schemes. Then, a taxonomy of the investigated approaches based on their applied metaheuristic algorithms is presented and in each category, schemes are studied and their main contributions and properties as well as their limitations are discussed. At last, a comparison of the techniques, tools, and methods that have been used in the studied schemes are provided along with the concluding remarks and future research directions.

An enhanced approach towards improving the performance of embedding memory management units into Network-on-Chip

Network-on-Chip (NoC) initiates the design procedure of interconnection network into SoC - System-on-Chip. The current technique overcomes the drawbacks of traditional bus-based SoC, for instance, poor scalability, small-link bandwidth, and large delay. The network-on-Chip systems required minimum buffering space and low-latency requirements. Here, the FIFO buffer is utilized as a virtual channel to evade deadlock issues and thus enhances throughput. The current research focused on an enhanced toward improving Embedding-Memory-management- Units performance into Network-on-Chip. Here, the 3D NoC was considered in the study for Noc improvement and has achieved high performance. Further, A first-in-first-out (FIFO) buffer was used in NoC routers to store the data packets temporarily. Eventually, the RAM -random access memory was proposed that serves as a link between the crossbar switch and the input ports. The simulation result of the current research results in only 0 to 16 memory for data storage in a stack out of 64, with the almost empty signal being high.

TB-TBP: a task-based adaptive routing algorithm for network-on-chip in heterogenous CPU-GPU architectures

With the rapid development of heterogeneous network-on-chip (NoC), a vast amount of shared resources are integrated into NoC. Intense resource competition exists between CPUs and GPUs, leading to congestion and a decrease in overall network performance. Reasonable node placement can minimize network conflicts at the topology level. This paper first discusses the placement of shared last-level cache and memory controller, then selects a more rational placement method and optimizes the path. To solve the hot spots problem in center placement method, a task-based routing algorithm is designed to plan the path. Simulation results demonstrate that, compared to the traditional routing algorithm, the overall network latency is reduced by 9%, and the CPU performance is improved by 13.6%. Furthermore, a dynamic task-based routing algorithm is proposed. Compared to the static task routing algorithm, the overall network latency is reduced by 2.08%, and the CPU performance is improved by 4.09%.

OECS: a deep convolutional neural network accelerator based on a 3D hybrid optical-electrical NoC

Various emerging technologies have been proposed and applied to deep convolutional neural networks (DCNNs) to enhance their execution efficiency and accuracy while reducing the number of parameters. However, previous dataflow-based DCNN accelerators have primarily focused on accelerating the convolution (CONV) layer while reducing the overhead of data movement through specific data reuse strategies to improve performance. When deploying these emerging DCNNs in conventional accelerators, frequent data access from both the external memory and internal processing units of the accelerator can result in significant data movement overhead, leading to decreased acceleration performance. To address these challenges, this paper proposes a novel three-dimensional hybrid optical-electrical network-on-chip (NoC) accelerator called the optical-electronic channel-stationary system (OECS). OECS leverages a channel stationary (CS) calculation mode and stay-at-local data storage strategy to minimize the movement and processing of all data in the local processing element (PE). This strategy reduces data movement between each PE in the accelerator and between the accelerator and external memory, resulting in improved acceleration performance. Simulation results demonstrate that, compared to state-of-the-art accelerators, OECS achieves a 53% improvement in execution speed and saves approximately 44% of energy consumption associated with data movement.

On-chip multifunctional self-configurable quadrilateral MZI network

Photonic integrated circuits have garnered significant attention in recent years. To enhance the functional versatility of these devices, researchers have introduced the concept of reconfiguration into photonic integrated circuits. Inspired by field programmable gate arrays in the electrical domain, programmable photonic chips employing various topologies have been developed. However, users still encounter challenges when utilizing these devices, as they need to understand the internal structure and principles of the chip and individually adjust the tunable basic units within the topology network. In this paper, we employ the quadrilateral topological network based on the on-chip Mach–Zehnder interferometer as a black box to realize a highly self-reconfigurable optical signal processor. By leveraging this approach, we achieve positive real-valued matrix computation, optical routing, and low-loss optical energy splitting. Our demonstration effectively showcases the immense potential of on-chip programmable photonic waveguide meshes.

Dynamically Scalable NoC Architecture for Implementing Run-Time Reconfigurable Applications.

The paper proposes two architectures for a dynamically scalable network-on-chip (NoC) for dynamically reconfigurable intellectual properties (IPs) to save power. The first architecture is a run-time scalable column-based NoC, where the columns of the NoC are scaled up and down at run-time depending on the demands to connect reconfigurable IPs. The second architecture is an extension of the first, where both the rows and columns of the NoC are dynamically scaled up and down on demand. A robust control manager is developed to control the IP and sub-NoC reconfigurations by optimizing the reconfiguration costs. The proposed architectures have been implemented and tested in actual prototypes on a Virtex 6 FPGA mounted on the ML605 board. The results show that dynamically scalable architectures are capable of significant power reduction as compared to traditional static architectures for the same size of the NoC. It is anticipated that the scalable NoC can be very useful for sharing the FPGA resources among IPs at runtime.

Robust topological valley-locked waveguide transport in photonic heterostructures

Topological valley-locked edge state has arisen a rapidly developing research topic in photonics for its gapless dispersion and immunity against intervalley scattering. However, valley-locked edge state is usually confined around the domain walls of valley photonic crystals (VPhCs) with different topological invariants, which decreases the flexibility of valley photonic devices and limits its application in on-chip integration. Here we propose a topological valley-locked waveguide (TVLW) with a width degree of freedom (DOF) by using a photonic heterostructure where a VPhC characterized by Dirac cones is sandwiched by two VPhCs with opposite valley Chern numbers. The TVLW is available for the transmission of waveguide states which maintain the properties of momentum-valley locking and robustness to defects. Taking advantage of these properties of TVLWs, we design a topological energy concentrator for field enhancement and a topological power splitter with an arbitrary splitting ratio by introducing the rotation angle of channels as a new DOF. Compared with conventional waveguides, the proposed TVLWs with tunable mode-width are more flexible to interface with the existing photonic devices, which provide broad application prospects in on-chip communication and photonic integrated networks.

Secure Routing Framework for Mitigating Time-Delay Trojan Attack in System-on-Chip

In order to meet the complex requirements of the semiconductor market, the packet-based on-chip interconnect IP; Network-on-Chip (NoC) used in System-on-Chips (SoCs), provides provisions for in-house designers to customise the NoC design. This opens a backdoor for the adversary to insert malicious circuits to deploy attacks like exposing cryptography keys, resource depletion attacks, etc. A malicious implant, such as a Hardware Trojan (HT) on NoC that initiates a delay-of-service attack, can tamper with the system and the application performance. In this work, we model an HT that mounts a time-delay attack in a NoC by violating the path selection strategy used by the route compute unit of the adaptive NoC router. Our experimental analysis shows that the proposed HT increases the packet latency by 14.5% and degrades the system performance (IPC) by 15% over the Baseline. For HT detection, we propose a framework that uses packet traffic analysis and path monitoring to localise the HT. We also propose a security wrapper module for the route compute unit that suppresses the effect of HT with an average IPC reduction of only 1.8% over the Baseline.

Design and Analysis of Four Port Router for Network-On-Chip Applications

System-On-Chip (SoC) is a popular VLSI technology that integrates multiple devices onto a single chip. The Network-On-Chip (NOC) concept, which is a novel paradigm in sophisticated System-On-Chip designs that offers efficient communication throughout the on-chip networks, is used to communicate amongst various devices. The router is the main component in an NoC architecture that is responsible for routing information. Packets are sent through a network by an NoC made up of routers. A routing algorithm divides packets into flow control digits (flits) and determines their paths. The placement of routers is determined by the network topology. In the present work, the main target is to design and analyse the router, which is primarily based on a number of critical factors, including topology, routing algorithm, and packet format. The performance of the suggested router is evaluated and compared to that of the Conventional Wormhole Router (CWHR) with respect to power and slack time (ST). When compared to a traditional wormhole router, the proposed router architecture has 18% less slack. As a result, total power consumption is reduced by 29.3% as compared to traditional wormhole architecture. The architecture is synthesized using Cadence Encounter RTL Compiler using standard 65nm technology.

ETA: An Efficient Training Accelerator for DNNs Based on Hardware-Algorithm Co-Optimization.

Recently, the efficient training of deep neural networks (DNNs) on resource-constrained platforms has attracted increasing attention for protecting user privacy. However, it is still a severe challenge since the DNN training involves intensive computations and a large amount of data access. To deal with these issues, in this work, we implement an efficient training accelerator (ETA) on field-programmable gate array (FPGA) by adopting a hardware-algorithm co-optimization approach. A novel training scheme is proposed to effectively train DNNs using 8-bit precision with arbitrary batch sizes, in which a compact but powerful data format and a hardware-oriented normalization layer are introduced. Thus the computational complexity and memory accesses are significantly reduced. In the ETA, a reconfigurable processing element (PE) is designed to support various computational patterns during training while avoiding redundant calculations from nonunit-stride convolutional layers. With a flexible network-on-chip (NoC) and a hierarchical PE array, computational parallelism and data reuse can be fully exploited, and memory accesses are further reduced. In addition, a unified computing core is developed to execute auxiliary layers such as normalization and weight update (WU), which works in a time-multiplexed manner and consumes only a small amount of hardware resources. The experiments show that our training scheme achieves the state-of-the-art accuracy across multiple models, including CIFAR-VGG16, CIFAR-ResNet20, CIFAR-InceptionV3, ResNet18, and ResNet50. Evaluated on three networks (CIFAR-VGG16, CIFAR-ResNet20, and ResNet18), our ETA on Xilinx VC709 FPGA achieves 610.98, 658.64, and 811.24 GOPS in terms of throughput, respectively. Compared with the prior art, our design demonstrates a speedup of 3.65x and an energy efficiency improvement of 8.54x on CIFAR-ResNet20.

Hybrid, Asymmetric and Reconfigurable Input Unit Designs for Energy-Efficient On-Chip Networks

The complexity and scale of Networks-on-Chip (NoCs) are growing as more processing elements and memory devices are implemented on chips. However, under strict power budgets, it is also critical to lower the power consumption of NoCs for the sake of energy efficiency. In this paper, we therefore present three novel input unit designs for on-chip routers attempting to shrink their power consumption while still conserving the network performance. The key idea behind our designs is to organize buffers in the input units with characteristics of the network traffic in mind; as in our observations, only a small portion of the network traffic are long packets (composed of multiple flits), which means, it is fair to implement hybrid, asymmetric and reconfigurable buffers so that they are mainly targeting at short packets (only having a single flit), hence the smaller power consumption and area overhead. Evaluations show that our hybrid, asymmetric and reconfigurable input unit designs can achieve an average reduction of energy consumption per flit by 45%, 52.3% and 56.2% under 93.6% (for hybrid designs) and 66.3% (for asymmetric and reconfigurable designs) of the original router area, respectively. Meanwhile, we only observe minor degradation in network latency (ranging from 18.4% to 1.5%, on average) with our proposals.

A high-performance fully adaptive routing based on software defined network-on-chip

Adaptive routing techniques have been proven to be effective solutions for handling network congestion and enhancing the performance of Network-on-Chip (NoC). Traditional adaptive routing algorithms may degrade flexibility and lead to the issue of high hardware implementation overhead. In this paper, we propose a fully adaptive routing (FAR) based on Software Defined NoC (SDNoC) to address these issues. The proposed FAR decouples path selection from packet forwarding. The routing path is determined by software techniques in the control layer according to the global congestion status and is encapsulated into the packet to control the forwarding of the packet. Evaluation results show that the proposed FAR yields an improvement of performance over the typical routing schemes in average packet latency and saturation throughput up to 8.2% and 6.1% respectively. The layout area and power consumption are at least 6.2% and 3.9% less compared with the typical routing schemes as well.

A Review Paper on Multi-tasking on Network on Chip(NOC)

Now a days development of Integrated Circuit technology is composed of multiple cores in a single chip called System on Chip (SoC). The technology has advanced from to single to multi core so as to improve the performance. These require effective communication, High performance, flexibility, scalability and design friendly interconnection. Before the initiation of Network on Chip (NoC), interconnection is based on wire and they cannot encounter ever increasing demand for on chip systems due to lack of scalability. NoC has several advantages such as high bandwidth, low power consumption and scalability. The interconnection among multiple cores on a chip have impact on communication and performance of chip design in terms of collision occurrence, noise, and pocket loss ratio and delay. Therefore, it is valuable studying the different multitasking algorithms. This paper reviews the widespread NoC algorithms and also few recent inclinations in interconnection networks. The area, power consumption, design complexity and congestion are studied to review the performance and summarize their merits.

Built-in Self-prevention (BISP) for runtime ageing effects of TSVs in 3D ICs

The adoption of Through-Silicon-Vias (TSVs) in Three-Dimensional Integrated Circuits (3D ICs) is gaining momentum in the industry, thanks to the numerous advantages it offers over traditional 2D ICs. However, TSVs are susceptible to defects during their formation, die stacking, and operational lifespan, leading to reliability issues in 3D ICs. While existing approaches have focused on addressing assembly and stacking yield losses, the runtime failure caused by Electro-migration (EM) remains a significant challenge in commercializing TSV-based 3D ICs. Detecting and monitoring TSV defects require an expensive on-chip sensor network, making it crucial to implement a cost-effective TSV defect prevention and detection scheme. This paper introduces a runtime Built-in Self-prevention (BISP) scheme that significantly extends TSV lifetime. The proposed method employs a repair circuit to rectify post-manufacturing TSV defects, resulting in minimal hardware costs. Furthermore, the combined repair and prevention solution introduces a delay overhead of less than 0.5 ns, ensuring compliance with timing constraints.