On-chip Capacitor Research Articles

A Fast-Transient-Response NMOS LDO with Wide Load-Capacitance Range for Cross-Point Memory

In this paper, a fast-transient-response NMOS low-dropout regulator (LDO) with a wide load-capacitance range was presented to provide a V/2 read bias for cross-point memory. To utilize the large dropout voltage in the V/2 bias scheme, a fast loop consisting of NMOS and flipped voltage amplifier (FVA) topology was adopted with a fast transient response. This design is suitable to provide a V/2 read bias with 3.3 V input voltage and 1.65 V output voltage for different cross-point memories. The FVA-based LDO designed in the 110 nm CMOS process remained stable under a wide range of load capacitances from 0 to 10 nF and equivalent series resistance (ESR) conditions. At the capacitor-less condition, it exhibited a unity-gain bandwidth (UGB) of approximately 400 MHz at full load. For load current changes from 0 to 10 mA within an edge time of 10 ps, the simulated undershoot and settling time were only 144 mV and 50 ns, respectively. The regulator consumed 70 µA quiescent current and achieved a remarkable figure-of-merit (FOM) of 1.01 mV. At the ESR condition of a 1 µF off-chip capacitor, the simulated quiescent current, on-chip capacitor consumption, and current efficiency at full load were 8.5 µA, 2 pF, and 99.992%, respectively. The undershoot voltage was 20 mV with 800 ns settling time for a load step from 0 to 100 mA within the 10 ps edge time.

A Fully Integrated Multi-Phase Buck Converter With On-Chip Capacitor Dynamic Re-Allocation and Fine-Grained Phase-Shedding Techniques

This article presents a fully integrated multi-phase (MP) buck converter for on-chip power management units. A peak-and-valley differential sensing (PVDS) scheme based on a flying capacitor is proposed to evenly balance the multiple inductor currents without significant power overhead even under mismatches in inductances, parasitic series resistances, and control-signal skews among phases. In addition, dynamic re-allocation of on-chip capacitors enables an even more optimal frequency response and output ripple based on the number of activated phases. It also improves the chip area efficiency, resulting in a higher power density. The proposed DLL-based MP clock generation provides high granularity in the phase-shedding control to achieve high efficiency over a wide load range. The proposed fully integrated buck converter using six bond-wire inductors (1 nH) was fabricated in a 28-nm CMOS process. The chip running at a frequency of 400 MHz/phase can finely adjust the number of active phases by an integer step ranging from 1 to 6 through sensing a load current. A maximum power density of 1.23 W/mm2 and a peak efficiency of 83.7% were measured. This work achieved an ultra-fast dynamic voltage scaling (DVS) rate of 75 mV/ns.

A 135–150 GHz High-Power Frequency Tripler With Filtering Matching Network

This letter presents a 135–150 GHz high-efficiency and -power Schottky diode-based tripler integrated with low-loss waveguide filtering matching network. The active diode monolithic microwave integrated circuit (MMIC) is matched with two waveguide filters based on coupling matrix theory for a two-port network with complex impedance terminations. The filters and the active diode MMIC are integrated via the microstrip-to-waveguide transition, allowing a compact design on the relatively higher loss MMIC. In addition, an integrated on-chip capacitor is implemented to isolate dc and RF paths. The measurement shows that with 150–200 mW input power, the maximum conversion efficiency reaches 30.5% and the maximum output power is 47 mW. All filtering poles can be observed in measurements and the return loss achieves 10–15 dB within the passband. Good agreements between measurements and simulations demonstrate the validity of the design approach.

Scalable Self-Limiting Dielectrophoretic Trapping for Site-Selective Assembly of Nanoparticles.

The absence of a versatile, scalable, and defect-free bottom-up assembly of nanoparticles with high precision has been a longstanding roadblock facing the large-scale integration of diverse nanoparticle-based devices. To circumvent this roadblock, we present a self-limiting dielectrophoretic approach to precisely align nanoparticles onto an array of electrodes over a large area, assisted by lithographically defined capacitors in series with the electrodes. We have experimentally verified that the on-chip capacitor can reduce the probability of trapping multiple particles at a given site, as the electric field is greatly weakened after the first nanoparticle bridges the electrodes. A 70% yield of single-nanowire assembly has been achieved, and key factors limiting the current yield are discussed. The yield is expected to further increase by improving the nanoparticle-electrode contact and reducing the capillary force during the drying process. We also demonstrate the versatility of this approach for scalable and site-selective alignment of various nanoparticles.

A DC‐coupled 1.2 μW 0.012 mm 2 per channel neural amplifiers array with 75 dB system common mode rejection ratio and 300 mV common mode interference

System common mode rejection ratio (SCMRR) and common mode interference (CMI) range are two critical design specifications for multiple-channel neural recording front-end circuit in a freely moving animal experiment environment. This letter presents a neural amplifiers array consisting of 15 DC-coupled inverter-based recording channels, a reference channel and a shared voltage averaging circuit (VAC) with floating rail Common Mode Feedback (CMFB) to achieve high SCMRR and large CMI range. Meanwhile, power consumption and area are optimized through using simple inverter architecture and removal of the conventional on-chip AC-coupled capacitors. The proposed neural amplifier circuit is implemented in SMIC standard 0.18 μm CMOS process, achieving a typical 75 dB SCMRR (DC-80 Hz), 300 mV CMI range, 1.2 μW power consumption and 0.012 mm2 area per channel. The circuit is validated both by bench-top test and in-vivo animal experiment.

An Active EMI Cancellation Technique Achieving a 25-dB Reduction in Conducted EMI of LIN Drivers

Robustness to electromagnetic interference (EMI) is one of the primary design aspects of state of the art automotive ICs like System Basis Chips (SBCs) which provide a wide range of analog, power regulation and digital functions on the same die. One of the primary sources of conducted EMI on the Local Interconnect Network (LIN) driver output is an integrated switching DC-DC regulator noise coupling through the parasitic substrate capacitance of the SBC. In this paper an adaptive active EMI cancellation technique to cancel the switching noise of the DC-DC regulator on the LIN driver output to ensure electromagnetic compatibility (EMC) is presented. The proposed active EMI cancellation circuit synthesizes a phase synchronized cancellation pulse which is then injected onto the LIN driver output using an on-chip tunable capacitor array to cancel the switching noise injected via substrate. The proposed EMI reduction technique can track and cancel substrate noise independent of process technology and device parasitics, input voltage, duty cycle and loading conditions of the DC-DC switching regulator. The EMI cancellation system is designed and fabricated on a 180nm Bipolar-CMOS-DMOS (BCD) process with an integrated power stage of a DC-DC buck regulator at a switching frequency of 2MHz along with an automotive LIN driver. The EMI cancellation circuit occupies an area of 0.7 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , which is less than 3% of the overall area in a standard SBC and consumes 12.5 mW of power and achieves 25 dB reduction of conducted EMI in the LIN driver output’s power spectrum at the switching frequency and its harmonics.

A 16 MHz CMOS RC Frequency Reference With ±90 ppm Inaccuracy From −45 °C to 85 °C

This article presents a 16-MHz <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> frequency reference implemented in a standard 180-nm CMOS process. It consists of a frequency-locked loop (FLL) in which the output frequency of a digitally controlled oscillator (DCO) is locked to the frequency-phase characteristic of a Wien bridge <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> filter. Since it is made from on-chip resistors and capacitors, the filter’s characteristic is temperature dependent. To compensate for this, the control signal of the DCO is derived by digitizing the filter’s output phase and combining it with the digital output of a Wheatstone bridge temperature sensor. After a two-point trim, this digital temperature compensation scheme achieves an inaccuracy of ±90 ppm from −45 °C to 85 °C. The frequency reference draws 220 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> from a 1.8-V supply, with a supply sensitivity of 0.12%/V and a 320-ppb Allan Deviation floor for a 10-s stride.

A 0.5–1 V, −68 dB Power Supply Rejection Capacitorless Analog LDO Using Voltage-to-Time Conversion in 28-nm CMOS

This article proposes an analog low-dropout (LDO) regulator using the voltage-to-time conversion technique to achieve high power-supply-rejection (PSR) at low supply voltages of less than 1 V. Integrating the time-domain signal into the current using a charge pump (CP) provides infinite dc gain, in principle, so that good regulation and high PSR can be achieved. Furthermore, a slew enhancement path using a time-converted signal is proposed to obtain a fast transient response even at low power supply voltages, and an auxiliary feedforward circuit has also been included to ensure wide load range stability. The proposed LDO designed to drive a 100-pF on-chip load capacitor and 150-mA load current was fabricated on a 28-nm CMOS process. The test measurement results show that the proposed LDO can operate in the 0.5–1-V input voltage range and achieved a high PSR of −52 to −68 dB at 1 kHz and −20 to −30 dB at 1 MHz, corresponding to the input voltage. Owing to the slew enhancement path, undershoot and overshoot were suppressed to 94 and 91 mV, respectively, for a 149-mA, 40-ns load current step.

High-Q On-Chip Capacitors Featuring “Self-Inductance Cancellation” for RF and mm-Wave Applications

In this letter, we are reporting on the characterization of the on-chip metal–oxide–metal (MOM) capacitors that use “self-inductance cancellation” technique resulting in high-performance operation in radio frequency (RF)/millimeter-wave (mm-wave) regime. The utilized method helps mitigate the mutual magnetic induction between the metal fingers of a MOM capacitor while they are placed in proximity to each other, by controlling the direction of the RF current flow. More than two times inductance cancellation is achieved, thus resulting in an increase of the self-resonance frequency and quality factor ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$ </tex-math></inline-formula> -factor) of the RF capacitor. The test structures are fabricated using Intel 16 FinFET technology, where postsilicon data show a good agreement between the theory and simulation. This methodology is CMOS compatible and is applicable to RF/mm-wave circuits that employ RF capacitors toward improving the RF system performance.

MOSFET-C transimpedance filters with center frequency tunability feature

ABSTRACT In this paper, seven different MOSFET-C transimpedance filters with their corresponding transfer functions and basic filter specifications, are provided. Presented designs show second-order standard band-pass, low-pass, or high-pass characteristics. Moreover, some filters provide both low-pass and band-pass characteristics. Especially, having a tunability feature makes a design more useful and applicable for various communication and instrumentation systems. The selected filter topology was biased under various biasing conditions to tune central frequency by keeping bandwidth constant. To elaborate the design with different aspects, we checked its small-signal performance by introducing both changing temperature and implementation errors. The theoretical results are in detail verified by numerous simulations using Cadence IC6 Spectre analog design environment. In the design, transistors with 1.8 V supply voltage were used and modelled by the SilTerra Malaysia 180 nm CMOS process parameters. The implemented layout, including metal-insulator-metal on-chip capacitors, occupies an area of 175 μm × 75 μm, while the total power consumption of the filter is found to be only 128.86 μW.

Physical Modeling of Monolithic Self-Rolled-Up Microtube Interdigital Capacitors

This article presents a physical model for monolithic self-rolled-up microtube interdigital capacitors and elaborates their working mechanisms in comparison to on-chip planar interdigital capacitors. Besides the high-frequency phenomena such as the skin effect in thin, wide metal films, the model accounts for the complexities resulting from all possible 3-D electrode configurations, such as the inner diameter-dependent overlapping capacitances and edge capacitances between electrodes, as well as parasitic inductances within the rolled-up structure between the fingers, for integer and noninteger number of turns. The model is validated by the measured results of fabricated self-rolled-up membrane (S-RuM) interdigital capacitors over a wide range of layout and process parameters. This fully enables the structural design optimization for electrical performance of this 3-D device architecture.

Spectroscopic Sensing Method of Liquid Permittivity with On-Chip Capacitor

A liquid permittivity sensing method is proposed, which is based on measuring the S21 of an on-chip capacitor submerged in a material under test (MUT). The real part of permittivity can be estimated from ɛ′ – |S21| fitted relation in the frequency range of 100 MHz–5 GHz, which are pre-calibrated with four kinds of known materials. The on-chip capacitor is realized with a top metal in a complementary metal oxide semiconductor (CMOS) process, which has an inter-digitized structure featuring a small size of 150 μm × 195 μm. A simple circuit model of the capacitor is used to develop ɛ′ – |S21| relation with a fitting parameter. It shows less than 6.4% root-mean-square (rms) error of ɛ′ for propanol (C3H8O) at 100 MHz–5 GHz.

3-V Input, 70-V Output, Fully Integrated Hybrid Charge Pump

A novel integrated-circuit charge-pump (CP) voltage multiplier conceived for high multiplying factors is proposed. The solution exploits a mixed architecture which merges both Cockcroft-Walton and Dickson topologies, by using on-chip 12-V poly-poly capacitors and 3.3-V CMOS transistors, maximizing the output voltage at the minimum silicon size. The proposed CP has been designed to supply a fully integrated driver for miniaturized motors in Micro Electro Mechanical Systems (MEMS) technology. It is conceived to boost the power-supply voltage to values higher than those that either a Dickson (D), Fibonacci (F), Cockroft-Walton (CW) or Serial-Parallel (SP) fully integrated CPs can generate in the selected technology process. Indeed, the output voltage of the former two CPs is limited by voltage constraints of on-chip capacitors while the multiplication efficiency of the latter two is impacted by high values of on-chip stray capacitors. Specifically, the target > 70 V output voltage has to be internally generated starting from the provided minimum power-supply voltage of 3 V. Furthermore, a mathematical model is proposed to evaluate the open load output voltage and the equivalent output resistance.

Superhigh energy storage density on-chip capacitors with ferroelectric Hf0.5Zr0.5O2/antiferroelectric Hf0.25Zr0.75O2 bilayer nanofilms fabricated by plasma-enhanced atomic layer deposition.

Thanks to their excellent compatibility with the complementary metal-oxide-semiconductor (CMOS) process, antiferroelectric (AFE) HfO2/ZrO2-based thin films have emerged as potential candidates for high-performance on-chip energy storage capacitors of miniaturized energy-autonomous systems. However, increasing the energy storage density (ESD) of capacitors has been a great challenge. In this work, we propose the fabrication of ferroelectric (FE) Hf0.5Zr0.5O2/AFE Hf0.25Zr0.75O2 bilayer nanofilms by plasma-enhanced atomic layer deposition for high ESD capacitors with TiN electrodes. The effects of the FE/AFE thickness composition and annealing conditions are investigated, revealing that the Hf0.5Zr0.5O2 (1 nm)/Hf0.25Zr0.75O2 (9 nm) bilayer can generate the optimal ESD after optimized annealing at 450 °C for 30 min. This is mainly ascribed to the factor that the introduction of a 1 nm Hf0.5Zr0.5O2 layer enhances the formation of the tetragonal (T) phase with antiferroelectricity in the AFE Hf0.25Zr0.75O2 layer as well as the breakdown electric field of the bilayer while fixing the FE/AFE bilayer thickness at 10 nm. As a result, a ESD as high as 71.95 J cm-3 can be obtained together with an energy storage efficiency (ESE) of 57.8%. Meanwhile, with increasing the measurement temperature from 300 and 425 K, the capacitor also demonstrates excellent stabilities of ESD and ESE. In addition, superior electrical cycling endurance is also demonstrated. Further, by integrating the capacitor into deep silicon trenches, a superhigh ESD of 364.1 J cm-3 is achieved together with an ESE of 56.5%. This work provides an effective way for developing CMOS process-compatible, eco-friendly and superhigh ESD three-dimensional capacitors for on-chip energy storage applications.

A GMSK/PAM4 Multichannel Magnetic Human Body Communication Transceiver

This letter presents a dual-mode multichannel transceiver implemented with low path loss offered by magnetic human body communication (mHBC) toward ultraefficient body-area networking. Two spectral-efficient modulation schemes: 1) Gaussian minimum-shift keying (GMSK) and 2) 4-level pulse-amplitude modulation (PAM4), are used to reduce interference on adjacent channels. A power oscillator is used to efficiently generate both GMSK- and PAM4-modulated magnetic fields while multichannel selection is implemented by on-chip capacitor tuning and an analog PLL, enabling 5 and 10 Mb/s data for GMSK and PAM4, respectively. The transmitter achieves an efficiency of 15.5 and 19.4 pJ/bit, while the receiver consumes 4.6 and 2.7 pJ/bit for GMSK and PAM4, respectively.

A Compact CMOS Broadband Bidirectional Digital Transceiver Frontend With Capacitor Bank and Transformer Matching Network Reuse

This article presents a fully integrated bidirectional class-G digital Doherty switched capacitor transmitter (TX) and N-path Quadrature receiver (RX) in CMOS. Through sharing on-chip capacitor banks, typically occupying a major portion of the digital TX or RX chip area, as well as the RF passive matching networks, the overall size can be radically reduced. Moreover, the overall performance could be further improved by eliminating the need for an integrated T/RX switch and its corresponding loss and area overhead. The class-G operation is used within the Doherty TX to increase the output power and backoff efficiency, while the capacitive stacking technique is used in the RX to increase the voltage gain. A transformer network is used to present the optimum impedance for both the parallel Doherty TX and RX mode of operation, as well as the class-G Doherty active load modulation. As a proof-of-concept, the joint bidirectional class-G digital Doherty switched-capacitor TX and N-path Quadrature RX through capacitor bank sharing is implemented in a 45-nm CMOS SOI process. The TX demonstrates a P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> 1dB bandwidth (BW) of 1.6-3.1 GHz, a fractional BW >63%, and peak output power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> ) of 22.5dBm at 2.4GHz. The peak drain efficiency (DE) of the TX is 49.5% at 1.8GHz and 41.5%/38.7%/31.6%/18.1% for the peak/2.5/6/12dB power back off (PBO) at 2.4GHz. The DE improvement compared to class-B PA is 1.24×/1.51×/1.72× at 2.5/6/12dB PBO. The TX is measured using 64-QAM/20MHz modulation without the use of AM-PM pre-distortion or pattern based DPD. It achieves an excellent -27.1dB EVM, -31.31dBc ACLR, 14.6dBm average P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> and 25.8% average DE at 1.6GHz. The RX achieves a noise figure (NF) of 7.6dB at 2.2GHz and a conversion gain of 17dB with a 12 MHz bandwidth. In addition, the proposed RX front-end achieves < -60 dBm LO leakage over the operating frequency range.

High PSRR Wide Supply Range Dual-Voltage Reference Circuit for Bio-Implantable Applications

On-chip systems are challenging owing to the limited size of the components, such as the capacitor bank in the rectifier. With a small on-chip capacitor, the output voltage of the rectifier might ring if the circuit experiences significant changes in current. The reference circuit is the first block after the rectifier, and the entire system relies on its robustness. A fully integrated dual-voltage reference circuit for bio-implantable applications is presented. The proposed circuit utilizes nonlinear current compensation techniques that significantly decrease supply variations and reject high-supply ripples for various frequencies. The reference circuit was verified using a 0.35 µm complementary metal-oxide semiconductor (CMOS) process. Maximum PSRR values of −112 dB and −128 dB were obtained. With a supply range from 2.8 to 12 V, the proposed design achieves 0.916 and 1.5 mV/V line regulation for the positive and negative reference circuits, respectively.

SecNVM: Power Side-Channel Elimination Using On-Chip Capacitors for Highly Secure Emerging NVM

Emerging nonvolatile memories (NVMs), such as resistive RAM (RRAM) and spin-transfer-torque RAM (STTRAM), present exciting opportunities for data storage applications and offer improved access speeds, retention times, power consumption, and scalability. However, these technologies leak the Hamming weight of data through power side-channel during read and write operations. We propose a technique leveraging on-chip capacitor and voltage regulator (VR) that powers the NVM read/write operations. The side-channel leakage is eliminated due to the isolation of memory array from the external power supply during read/write operations. The residual charge on capacitor bank is discarded safely to prevent information leakage during capacitor recharging. The VR ensures a steady voltage during the entire read/write operations even though the capacitor discharges. The design presents a performance (instructions per cycle) degradation of 0.53%-1.2% under parsec and splash-2 benchmarks and incurs an area overhead of ~ 3.54×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> % and an energy overhead of ~ 3.05 ×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> % for a 4-Mb RRAM memory array. For a 64-bit word, the design improves security by 2.7 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">19</sup> × to 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">64</sup> ×. SecNVM should be used in small security-critical memory macros to limit the overhead. SecNVM is generic and could protect any security module such as encryption engines, against power side-channel attacks.

A Novel Balanced Frequency Tripler With Improved Power Capacity for Submillimeter-Wave Application

This letter reports on the demonstration of a 204-232-GHz Schottky diode frequency tripler based on the novel balanced configuration, which provides superior power handling to traditional approaches. This tripler adopts a novel balanced configuration, which utilizes a symmetrical circuit to achieve the improved amplitude and phase balance, as well as dc bias without any on-chip capacitor. Thus, this tripler features improved power capacity by multiple diodes and better conversion efficiency. At room temperature, the fabricated tripler exhibits a 22.1% peak conversion efficiency for a nominal input power of around 300-560 mW. This tripler can deliver maximum power of 84.5 mW and 16.2% conversion efficiency for 521-mW input power at 226.8 GHz.

A Reconfigurable Capacitive Power Converter With Capacitance Redistribution for Indoor Light-Powered Batteryless Internet-of-Things Devices

In this article, a reconfigurable capacitive power converter with capacitance redistribution for indoor light-powered batteryless Internet-of-Things (IoT) devices is presented. The proposed converter is capable of redistributing the capacitance among two charge pump stages to efficiently utilize the harvested energy and further powering milliwatt-powered loading circuits occasionally. Moreover, the proposed converter is capable of storing and reusing the harvested energy to cope with the power demand under different operating modes. The first charge pump stage stores the excessive energy produced by a photovoltaic (PV) cell to the storage capacitor using a maximum power point tracking (MPPT) technique under low-output power demand, whereas the second stage provides a regulated 1.5-V output voltage. The variation of the PV input voltage (from 0.45 to 0.9 V) is compensated by employing a converter, whose power stage consists of 16 reconfigurable charge pump submodules with 1.5 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> and 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> conversion ratios and a digital low-dropout (DLDO) regulator. By implementing the proposed capacitance redistribution, the on-chip capacitance can be reduced by 46.7%. The proposed capacitive power converter is fabricated using a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process. The measured results show a peak-power conversion efficiency of 92.4%, 65.7%, and 69.5% for 1 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> , 1.5 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> , and 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> conversion ratios, respectively.