3-V Input, 70-V Output, Fully Integrated Hybrid Charge Pump

Abstract

A novel integrated-circuit charge-pump (CP) voltage multiplier conceived for high multiplying factors is proposed. The solution exploits a mixed architecture which merges both Cockcroft-Walton and Dickson topologies, by using on-chip 12-V poly-poly capacitors and 3.3-V CMOS transistors, maximizing the output voltage at the minimum silicon size. The proposed CP has been designed to supply a fully integrated driver for miniaturized motors in Micro Electro Mechanical Systems (MEMS) technology. It is conceived to boost the power-supply voltage to values higher than those that either a Dickson (D), Fibonacci (F), Cockroft-Walton (CW) or Serial-Parallel (SP) fully integrated CPs can generate in the selected technology process. Indeed, the output voltage of the former two CPs is limited by voltage constraints of on-chip capacitors while the multiplication efficiency of the latter two is impacted by high values of on-chip stray capacitors. Specifically, the target > 70 V output voltage has to be internally generated starting from the provided minimum power-supply voltage of 3 V. Furthermore, a mathematical model is proposed to evaluate the open load output voltage and the equivalent output resistance.