On-axis Si Research Articles

Structural Study of the Innovative 3C-SiC/Si/3C-SiC/Si Heterostructure for Electro-Mechanical Applications

In this work, we report the growth of a 3C-SiC layer oriented along the [111] direction on Si (110)/3C-SiC(001)/Si (001) heterostructure. The growth of the complete layer stack occurs in one deposition run in a Chemical Vapor Deposition (CVD) reactor on on-axis Si (001) substrate. The structural properties of the 3CSiC(111) layer are discussed and the impact of the first 3C-SiC layer on the subsequent growth is highlighted. The 3C-SiC(111) top layer shows two domains rotated by 90o around the growth direction directly linked to the domains rotation in the Si epilayer underneath it. Furthermore, μtwins and stacking faults are present on the inclined (111) planes in the 3C-SiC epilayer.

Kinetic surface roughening and wafer bow control in heteroepitaxial growth of 3C-SiC on Si(111) substrates.

A thin, chemically inert 3C-SiC layer between GaN and Si helps not only to avoid the “melt-back” effect, but also to inhibit the crack generation in the grown GaN layers. The quality of GaN layer is heavily dependent on the unique properties of the available 3C-SiC/Si templates. In this paper, the parameters influencing the roughness, crystalline quality, and wafer bow are investigated and engineered to obtain high quality, low roughness 3C-SiC/Si templates suitable for subsequent GaN growth and device processing. Kinetic surface roughening and SiC growth mechanisms, which depend on both deposition temperature and off-cut angle, are reported for heteroepitaxial growth of 3C-SiC on Si substrates. The narrower terrace width on 4° off-axis Si enhances the step-flow growth at 1200 °C, with the roughness of 3C-SiC remaining constant with increasing thickness, corresponding to a scaling exponent of zero. Crack-free 3C-SiC grown on 150-mm Si substrate with a wafer bow of less than 20 μm was achieved. Both concave and convex wafer bow can be obtained by in situ tuning of the deposited SiC layer thicknesses. The 3C-SiC grown on off-axis Si, compared to that grown on on-axis Si, has lower surface roughness, better crystallinity, and smaller bow magnitude.

Growth and characterization of an In0.53Ga0.47As-based Metal-Oxide-Semiconductor Capacitor (MOSCAP) structure on 300 mm on-axis Si (001) wafers by MOCVD

We report on the development of a metamorphic In0.53Ga0.47As-based heterostructure grown on 300mm on-axis Si (001) wafers by metal-organic chemical vapor deposition (MOCVD), and the fabrication of a Metal-Oxide-Semiconductor Capacitor (MOSCAP) with C–V characteristics and interfacial trap density (Dit) values comparable to those of an equivalent structure grown on an InP substrate. A 1.15µm thick GaAs/InP buffer with a defect density in the low 109cm−2 range and a surface roughness rms value <2nm was used to accommodate the large lattice mismatch between In0.53Ga0.47As and Si.

Si Surface Preparation for Heteroepitaxial Growth of SiC Using &lt;i&gt;In Situ&lt;/i&gt; Oxidation

To achieve high quality SiC growth on Si substrate, it is essential to get a smooth Si surface without forming SiC and graphitic islands during the surface cleaning and before the carbonisation process. In this paper, a novel in-situ surface cleaning method designed for the hetero-epitaxial growth of SiC on Si substrate is developed using a custom-made low-pressure chemical vapour deposition reactor. The results indicate that the combination of ramping in oxygen and subsequent flowing of SiH4 avoids the contamination of Si, enables the oxide layer to be removed smoothly, and subsequently creates a smooth Si surface with regular atomic steps. SiC grown on off-axis Si has better crystallinity and significantly smaller roughness than that grown on on-axis Si.

Influence of Trench Width on III-V Nucleation during InP Selective Area Growth on Patterned Si(001) Substrate

The integration of III/V materials onto Si substrates is of significant interests for microelectronic and optoelectronic applications. The utilization of the selective epitaxial growth (SEG) on patterned Si substrates by metalorganic vapor phase epitaxy (MOVPE) is proved as a valuable solution for the heteroepitaxy of III-V semiconductors on Si thanks to the “defect trapping” by sidewalls. The demonstration of successful integration by the SEG in wide trenches (above 100nm) is extensively available in the literatures.[1-6] However, following scaling rules for Logic CMOS devices, new challenges are imposed on the heteroepitaxy inside nano-scaled trenches (i.e. sub-50nm trenches for FinFET devices). Therefore, in this study, the influence of trench width on nucleation behavior based on InP SEG in “V-groove” trenches[7,8] as an example, is discussed and analyzed via the proposal of a nucleation model according to the ex-situ morphology observation in the experiments. The evolution of morphology for the selective growth of InP in submicron “V-groove” trenches on on-axis Si(001) substrates is characterized by SEM and AFM. Due to the high lattice mismatch between InP and Si, the typical evolution of 3D islands growth mode in both wide and narrow trenches is identified. The comparison of nominally 40nm to both 150nm and 500nm wide trenches indicates that there is an evolution lag for islands coalescence in narrower trenches. This is the reason for discontinuous topology and highly defective layers obtained in sub-50nm trenches. We believe that one possible mechanism attributing to this lag is induced by greater inter-island distance in narrower trenches. Therefore, we propose a nucleation model to evaluate the influence of trench width on the inter-island distance, suggesting that the scaling relationship between the critical inter-island distance and trench width is theoretically predicted as L* ~W-1/(2i*+4) if W≤2L*in the surface-diffusion limited regime. This understanding is of critical importance for the uniform growth inside nano-trenches for the heteroepitaxy of mismatched III/V compounds onto Si substrates, where the 3D island growth mode dominates in most cases.ACKNOWLEDGMENTSThis work is supported by IMEC Industrial Affiliation Program. The present authors would like to thank the Logic Program and Management, partners.References 1 W.J. Choi and P. Daniel Dapkus, J. Cryst. Growth 195, 495 (1998). 2 G. Wang, M.R. Leys, N.D. Nguyen, R. Loo, G. Brammertz, O. Richard, H. Bender, J. Dekoster, M. Meuris, M.M. Heyns, and M. Caymax, J. Electrochem. Soc. 157, H1023 (2010). 3J.Z. Li, J. Bai, J.M.Hydrick, J.G. Fiorenza, C.Major, M. Carroll, Z. Shellenbarger and A. Lochtefeld, ECS Trans. (2009), pp. 887–894. 4 C. Merckling, N. Waldron, S. Jiang, W. Guo, O. Richard, B. Douhard, a. Moussa, D. Vanhaeren, H. Bender, N. Collaert, M. Heyns, a. Thean, M. Caymax, and W. Vandervorst, J. Appl. Phys. 114, 033708 (2013). 5 S. F. Cheng, L. Gao, R. L. Woo, a. Pangan, G. Malouf, M.S. Goorsky, K.L. Wang, and R.F. Hicks, J. Cryst. Growth 310, 562 (2008). 6 Y. Dong, Y.L. Okuno, and U.K. Mishra, J. Cryst. Growth 260, 316 (2004). 7M. Paladugu, C. Merckling, R. Loo, O. Richard, H. Bender, J. Dekoster, W. Vandervorst, M. Caymax, and M. Heyns, Cryst. Growth Des.12(10), 4696 (2012). 8 C. Merckling, N. Waldron, S. Jiang, W. Guo, N. Collaert, M. Caymax, E. Vancoille, K. Barla, a. Thean, M. Heyns, and W. Vandervorst, J. Appl. Phys. 115, 023710 (2014).

Misorientation dependent epilayer tilting and stress distribution in heteroepitaxially grown silicon carbide on silicon (111) substrate

The advantages and disadvantages of using off-axis substrates for heteroepitaxial growth of 3C-SiC on Si(111) substrates are investigated in this paper. 3C-SiC is deposited on on-axis and 4° off-axis 150mm Si(111) substrates using low pressure chemical vapour deposition. The dependence of surface morphology, roughness, crystallinity, alignment between the epilayer and the substrate, and film stress are evaluated using atomic force microscopy, X-ray diffraction, and wafer curvature measurement. Highly parallel steps are observed on both on-axis and off-axis Si substrates after surface preparation, yet step density is doubled and step height is much larger (>21 times of single step height) for 4° off-cut Si compared to on-axis Si. X-ray diffraction results indicate that SiC grown on on-axis Si substrates are well-aligned with the Si substrates, while the SiC grown on off-axis substrates are tilted positively by as large angle as 1.66°. The well-aligned SiC grown on on-axis Si substrate exhibits lower and uniform residual stress compared to the film grown on off-axis Si substrates, which exhibits a nonuniform distribution of higher stress. The stress distribution is found to be dependent on Si surface step direction and height. These misorientation dependent tilting and stress distribution mechanisms are expected to be applicable to other hetero-epitaxial growth systems with similar mismatch magnitude.

Low interface trap density Al2O3/In0.53Ga0.47As MOS capacitor fabricated on MOCVD-grown InGaAs epitaxial layer on Si substrate

A low interface trap density (Dit) Al2O3/In0.53Ga0.47As/Si MOS capacitor fabricated on an In0.53Ga0.47As heterostructure layer directly grown on a 300 mm on-axis Si(100) substrate by MOCVD with a very thin buffer layer is demonstrated. Compared with the MOS capacitors fabricated on the In0.53Ga0.47As layer grown on the lattice-matched InP substrate, the Al2O3/In0.53Ga0.47As MOS capacitors fabricated on the Si substrate exhibit excellent capacitance–voltage characteristics with a small frequency dispersion of approximately 2.5%/decade and a low interface trap density Dit close to 5.5 × 1011 cm−2 eV−1. The results indicate the potential of integrating high-mobility InGaAs-based materials on a 300 mm Si wafer for post-CMOS device application in the future.

Selective area growth of InP in shallow trench isolation on large scale Si(001) wafer using defect confinement technique

Heterogeneous integration of III–V semiconductors on Si substrate has been attracting much attention as building blocks for next-generation electronics, optoelectronics, and photonics. In the present paper, we studied the selective area epitaxial studies of InP grown on 300 mm on-axis Si (001) substrates patterned with Shallow Trench Isolation (STI) using the necking effect technique to trap crystalline defects on the sidewalls. We make use of a thin Ge buffer in the bottom of the trench to reduce interfacial strain at the interface and to promote InP nucleation. We could show here, by systematic analysis, the strong impact of the growth temperatures and pressures of the InP layer on the growth uniformity along the trench and crystalline quality that we correlated with resistance changes and interdiffusion measured in the III–V layer. The key challenge remains in the ultimate control of crystalline quality during InP selective growth in order to reduce defect density to enable device-quality III–V virtual substrates on large-scale Si substrates.

Characterization of epitaxially grown indium islands on Si(111)

Indium deposition onto on-axis Si(111) substrates and those miscut by 2.5° toward [112¯] was investigated. The Si substrates were held at temperatures ranging from room temperature up to 475 °C and the In deposition rate was varied by a factor of ∼20. All depositions were performed under ultrahigh vacuum conditions onto surfaces that were cleaned in situ. For growth at 100 °C and room temperature, the In films organize into three-dimensional islands. This result suggests that In deposition onto on-axis or miscut Si(111) substrates at temperatures lower than the In melting point of 157 °C is a viable route to form In seeds for epitaxial Si or Ge nanowire growth using the vapor–liquid–solid method. The morphology of the resultant island ensembles and their formation mechanisms are discussed.

Selective Area Growth of InP on On-Axis Si(001) Substrates with Low Antiphase Boundary Formation

We discuss the selective epitaxial growth of InP on patterned Si (001) substrates with Shallow Trench Isolation using a thin Ge buffer to facilitate InP nucleation. The main focus is the defect formation during epitaxial growth and to develop solutions to reduce defect density so that device-quality III-V virtual substrates can be realized on large-scale Si substrates. We compare the InP growth on on-axis and off-axis Si substrates. In the case of off-axis wafers, the formation of stacking faults / twins cannot be avoided, at least not at one of the four side-walls of the Shallow Trench Isolation. The formation of antiphase domain boundaries is reduced (but not yet completely eliminated) by engineering the local Ge surface profile. Further, the high density of Ge surface steps promotes step-flow growth mode instead of 3D growth during the growth of the InP seed layer. Finally, high aspect ratios (>2) allow to confine threading dislocations in the bottom of the trench.

(Invited) Selective Area Growth of InP on On-Axis Si(001) Substrates with Low Antiphase Boundary Formation

We discuss the selective epitaxial growth of InP on patterned Si (001) substrates with Shallow Trench Isolation using a thin Ge buffer to facilitate InP nucleation. The main focus is the defect formation mechanism during epitaxial growth and to develop solutions to reduce defect density so that device-quality III-V virtual substrates can be realized on large-scale Si substrates. We compare the InP growth on on-axis and off-axis Si substrates. In the case of off-axis wafers, the formation of stacking faults / twins cannot be avoided, at least not at one of the four STI side-walls. The formation of antiphase domain boundaries is reduced (but not yet completely eliminated) by engineering the local Ge surface profile. Further, the high density of Ge surface steps promotes step-flow growth mode instead of 3D growth during the growth of the InP seed layer. Finally, high aspect ratios (>2) allow to confine threading dislocations in the bottom of the trench.

Selective Area Growth of InP on On-Axis Si(001) Substrates with Suppressed Antiphase Boundary Formation

not Available.

Growth and Optical Properties of InGaAs via Ge-Based Virtual Substrates: A New Chemistry Based Strategy

In this study, we report the epitaxial integration of InGaAs films on Ge/Si(100) virtual substrates for photonic applications. Ge buffer layers with thicknesses of 400-700 nm were grown directly on vicinal (5 degrees miscut) and on-axis Si (100) wafers using a new low-temperature, chemistry-based approach that allows unprecedented control of film microstructure, morphology and purity at CMOS-compatible conditions. In0.01Ga0.49As0.50 films lattice matched to Ge and with thicknesses in the range of 800-2500 nm were then deposited on both Ge/Si substrates and bulk Ge wafers using industrial MOCVD. All materials were characterized by high-resolution X-ray diffraction, atomic force microscopy, transmission electron microscopy, time-resolved and steady-state photoluminescence, as well as cathodoluminescence. It is found that the properties of the InGaAs/Ge/Si(100) samples are comparable with those grown directly on bulk Ge platforms. Most importantly the films grown on miscut Ge templates are devoid of deleterious antiphase boundaries, making them promising candidates for large scale production of III-V photovoltaics.

Comparative study of InGaAs integration on bulk Ge and virtual Ge/Si(1 0 0) substrates for low-cost photovoltaic applications

Ge virtual substrates have been developed via low-temperature CVD based on new hydride molecular chemistry routes fully compatible with conventional CMOS. These are designed to enable integration of III–V compounds directly on Si and therefore have the potential to replace expensive Ge wafers in multijunction photovoltaics grown on the conventional 4–6″ format. Here we first describe in detail the protocols needed to produce defect-free and atomically flat Ge buffers with ∼0.25–3 μm thicknesses directly on vicinal (5°, 8°) and on-axis Si (1 0 0) substrates with up to 4″ diameters. Industrial MOCVD is then used to grow Ge-matched InGaAs films with thicknesses of 0.8–2.5 μm, both on our virtual substrates and on vicinal (6°) Ge wafers. A thorough characterization of the films’ morphological, structural, and optical properties allows a meaningful comparison of our best “virtual-substrate-grown” films with a mature and commercially available InGaAs technology on bulk Ge. Our studies confirm that the InGaAs films grown on Ge wafers exhibit the highest quality, followed closely by those grown on miscut Ge buffered Si. The latter films, in contrast to their on-axis counterparts, are devoid of antiphase-boundary defects and exhibit smoother surfaces and superior crystallinity, indicating the need for misoriented substrates to successfully integrate InGaAs on large area Si platforms. Collectively our work demonstrates the promise for transitioning our virtual substrate technology to the industrial scale production of photovoltaic III–IV films on Si(1 0 0) platforms.

P-Type Doping of Epitaxial 3C-SiC Layers on Silicon (001)

Single-crystalline 3C-SiC epitaxial layers were grown on on-axis Si (001) substrates by low-pressure hot-wall chemical vapour deposition. Aluminium from a trimethylaluminium (TMA) source was used for p-type doping. The atomic Al and carrier concentrations in the layers were determined as a function of the partial pressure of the TMA source gas. Secondary ion mass spectroscopy (SIMS), Hall-effect measurements at room temperature and four-point electrical resistivity method were applied to measure the atomic and electrically active Al concentrations. The crystalline perfection of the layers was characterized by high-resolution x-ray diffraction (HRXRD). At TMA-partial pressures ranging from 510-7 mbar up to 1.510-4 mbar corresponding aluminium concentrations from 21015 cm-3 up to 1.31019 cm-3 were measured in the epitaxial layers. On increasing the Al concentration from 1x1017 cm-3 to 1x1019 cm-3 the layer electrical resistivity decreases from 17 cm to 0.8 cm, while no influence on the crystalline quality of the layers was observed. The average full width at half maximum (FWHM) of the rocking curve for a 5µm thick 3C-SiC layer is about 500 arcsec. With increasing layer thickness (up to 16 µm) the FWHM of the rocking curve decreases to about 300 arcsec.

High Quality Single Crystal 3C-SiC(111) Films Grown on Si(111)

We have developed a high-quality growth process for 3C-SiC on on-axis (111)Si substrates with the ultimate goal to demonstrate high quality and yield electronic and MEMS devices. A single-side polished 50 mm (111)Si wafer was loaded into a hot-wall SiC CVD reactor for growth. The 3C-SiC process was performed in two stages: carbonization in propane and hydrogen at 1135°C and 400 Torr followed by growth at 1380°C and 100 Torr. X-ray diffraction rocking curve analysis of the 3C-SiC(222) peak indicates a FWHM value of 219 arcsec. This is a very interesting result given that the film thickness was only 2 µm, thus indicating that the grown film is of very high quality compared with published literature values. X-ray polar figure mapping was performed and it was observed that the micro twin content was below the detection limit. Therefore TEM characterization was performed in plan view to allow assessment of the stacking fault density as well as confirmation of the very low micro twin concentration in this film. TEM analysis indicates a low concentration of stacking faults in the range of 104 cm-1.

Influence of Growth Parameters on the Residual Strain in 3C-SiC Epitaxial Layers on (001) Silicon

3C-SiC epitaxial layers were grown on on-axis Si (001) substrates by low-pressure hot-wall chemical vapour deposition. Depending on the growth parameters, the residual strain in the 3C-SiC layer was seen to be tensile or compressive. In this work, the influence of parameters, such as growth temperature and C/Si ratio in the vapour phase, on residual strain and macroscopic layer bow is investigated. We found that the wafer bow changes from convex, at a deposition temperature of 1270° C, to concave at 1370° C. High resolution x-ray diffraction data indicate that the crystal-line perfection of the layers is lower for decreasing deposition temperature and increasing compres-sive strain. No remarkable influence of the C/Si ratio in the gaseous atmosphere on the FWHM of the rocking curve was observed.

Heteroepitaxial growth and characterization of 3C-SiC films on on-axis Si (1 1 0) substrates by LPCVD

Cubic SiC (3C-SiC) film has been deposited on Si (1 1 0) substrate by the low pressure chemical vapor deposition (LPCVD) with gas sources of SiH 4, C 3H 8 and carrier gas of H 2. The 3C-SiC crystalline film can be confirmed through the observations using reflection high-energy electron diffraction (RHEED) images. The X-ray diffraction (XRD) pattern and the rocking curve indicate that the (1 1 1) plane of SiC film is parallel to the surface of the Si (1 1 0) substrate and the film is of high crystallinity. The results of the field emission scanning electron microscope (FESEM) images show that the film has smooth surface morphology. Transmitted electron diffraction (TED) pattern and high resolution transmission electron microscope (HRTEM) image further confirm the high quality of the film.

Dependence of stacking fault and twin densities on deposition conditions during 3C-SiC heteroepitaxial growth on on-axis Si(0 0 1) substrates

Single-crystal 3C-SiC epilayers were grown on on-axis Si(0 0 1) substrates by low-pressure chemical vapor deposition. The dependence of the densities of stacking faults and twins on epilayer thicknesses and growth conditions—including the reactor pressure, the substrate temperature, and the inlet gaseous composition—were investigated by a series of experiments and simulations. Simple indexes were developed to predict the planar defect densities in terms of the flux ratio of adatoms on the deposition surface. The planar defect densities were significantly reduced with increasing the epilayer thickness until continuous surfaces with {1 0 0} planes were formed at 0.7 μm. The stacking fault density was a function of the surface flux ratio of carbon adatom to atomic hydrogen, while the twin density was a function of that of silicon adatom to atomic hydrogen. Those densities were decreased almost linearly with increases in the surface flux of atomic hydrogen at fixed flux values of carbon and silicon adatoms. The surface flux of atomic hydrogen was increased as either the reactor pressure was decreased or the substrate temperature was increased.

Formation of quasi-single-domain 3C-SiC on nominally on-axis Si(001) substrate using organosilane buffer layer

Quasi-single-domain 3C-SiC films have been successfully grown on nominally on-axis Si(001) substrate. The starting surface is either of 2×1 quasi-single-domain or of 2×1+1×2 double-domain. The point here is to use dc-resistive heating of the substrate and to form a low-temperature (650 °C) interfacial buffer layer using monomethylsilane (H3 C-SiH3). The dc resistive heating serves to form a single-domain Si(001)-2×1 or 1×2 starting surface or to develop a single-domain 3C-SiC(001)-2×3 or 3×2 surface on a 2×1+1×2 double-domain Si(001) substrate. When a single-domain Si(001) starting surface is utilized, it is not the dc polarity during growth but the surface reconstruction of the starting surface that determines the dominant domain in the 3C-SiC film. The thickness of the single-domain 3C-SiC film is as thin as ∼45–200 nm, which is about three orders of magnitude smaller than that required in a previous study (&amp;gt;5 μm).