Off-state Leakage Current Research Articles

True Nonvolatile High-Speed DRAM Cells Using Tailored Ultrathin IGZO.

Severe power consumption in the continuous scaling of Silicon-based dynamic random access memory (DRAM) technology quests for a transistor technology with a much lower off-state leakage current. Wide bandgap amorphous oxide semiconductors, especially indium-gallium-zinc-oxide (IGZO)exhibit many orders of magnitude lower off-state leakage. However, they are typically heavily n-doped and require negative gate voltage to turn off, which prevents them from true nonvolatile operation. The efforts on doping density reduction typically result in mobility degradation and high Schottky barriers at contacts, causing severe degradation of on-current and operation speed of the DRAM cells. Here, high-speed true nonvolatile DRAM cells are successfully demonstrated by deep suppression of doping density in the IGZO channel using in situ oxygen ion beam treatment and ohmic contact engineering by inserting a thin In-rich indium-tin-oxide (ITO) at contact regions. A record high on-current of 40µA µm-1 at a large positive threshold voltage of 1.78V enables the first true nonvolatile DRAM with the fastest write speed of 10ns and data retention up to 25 h under power interruption, five orders of magnitude higher than the previously projected values.

Charge Trapping and Emission Properties in CAAC-IGZO Transistor: A First-Principles Calculations.

The c-axis aligned crystalline indium-gallium-zinc-oxide field-effect transistor (CAAC-IGZO FET), exhibiting an extremely low off-state leakage current (~10-22 A/μm), has promised to be an ideal candidate for Dynamic Random Access Memory (DRAM) applications. However, the instabilities leaded by the drift of the threshold voltage in various stress seriously affect the device application. To better develop high performance CAAC-IGZO FET for DRAM applications, it's essential to uncover the deep physical process of charge transport mechanism in CAAC-IGZO FET. In this work, by combining the first-principles calculations and nonradiative multiphonon theory, the charge trapping and emission properties in CAAC-IGZO FET have been systematically investigated. It is found that under positive bias stress, hydrogen interstitial in Al2O3 gate dielectric is probable effective electron trap center, which has the transition level (ε (+1/-1) = 0.52 eV) above Fermi level. But it has a high capture barrier about 1.4 eV and low capture rate. Under negative bias stress, oxygen vacancy in Al2O3 gate dielectric and CAAC-IGZO active layer are probable effective electron emission centers whose transition level ε (+2/0) distributed at -0.73~-0.98 eV and 0.69 eV below Fermi level. They have a relatively low emission barrier of about 0.5 eV and 0.25 eV and high emission rate. To overcome the instability in CAAC-IGZO FET, some approaches can be taken to control the hydrogen concentration in Al2O3 dielectric layer and the concentration of the oxygen vacancy. This work can help to understand the mechanisms of instability of CAAC-IGZO transistor caused by the charge capture/emission process.

High Field-Effect Mobility and On/Off Current Ratio of p-Type ALD SnO Thin-Film Transistor

High-performance p-type thin-film transistors (TFTs) with high field-effect mobility and high on/off current ratios (Ion/Ioff) were fabricated by engineering the microstructure and surface morphology of the atomic layer-deposited (ALD) SnO channel layer. ALD SnO films grown at a deposition temperature of 225 °C showed excellent crystallinity and dense, smooth surfaces, which resulted in superior field-effect mobility of 6.13–7.24 cm2/V·s without using a high-temperature postannealing process. Optimization of the SnO channel thickness suppressed the off-state leakage current, which consequently yielded excellent TFT switching performance, with an Ion/Ioff value of 104–105. Additionally, backchannel passivation by the ALD Al2O3 film improved the subthreshold swing characteristics by reducing surface defect states. These results suggest that synergistic control of the microstructure, surface morphology, and thickness of ALD SnO channels is crucial for achieving high-performance p-type SnO TFTs.

Improved Off-State Leakage Current and Cutoff Frequency for AlGaN/GaN HEMT by Using Silicon-on-Insulator

An improvement in off-state leakage current and cutoff frequency for AlGaN/GaN high electron mobility transistors (HEMTs) is investigated. Raman spectroscopy confirms the low stress of GaN heterostructure grown on a silicon-on-insulator (SOI) substrate. The HEMT devices on SOI substrate show lower knee voltage (Vknee) and on-resistance (RON) compared to those on the high-resistive silicon (HR-Si) substrates by 20.8% and 30.4%, respectively. Off-state leakage current is reduced to 10−7 A mm−1, and the cutoff frequency (f t ) is increased by 19.2% as compared to HR-Si substrate. Thus, the GaN/SOI technology is proven to be a potential technology for high-frequency communication applications.

Study of GaN/AlGaN air structure gate HEMTs with high linearity for RF applications

The effect of a novel float gate HEMT with Gan cap under the gate is studied, its DC and RF characteristics have been shown by using SILVACO TCAD tool, as contrast, the simulation of the conventional T shape gate hemt, which fitting well with the experimental result, is also demonstrated. The proposed structure offers approximately 5 times improvement in power gain cutoff frequency (fmax) and current gain Cut-off frequency(fT) (from 5.68 and 3.7 GHz to 30.1 and 20.1 GHz, respectively.) and it greatly enhances the linearity of the Gan based HEMT, a much flatter curve for fT/fmax versus gate voltage are also shown, and 1 V positive threshold voltage shift is gained, meanwhile the off-state drain leakage current is also improved to a certain extend, therefor the hemt obtains a much higher Ion/Ioff ratio, without sacrificing the saturate current. Besides, the degradation of drain current due to the self-heating effect is also ameliorated by applying the novel structure. Finally, the corresponding electrical characteristic changes are systematically analyzed according to the energy band and other schematic diagrams, the physical insight is given in explaining the mechanism inside.

Effect of Acceptor Traps in GaN Buffer Layer on Breakdown Performance of AlGaN/GaN HEMTs.

In this paper, Silvaco TCAD software is used to simulate the buffer traps in AlGaN/GaN high electron mobility transistors (HEMTs), and its effects on the breakdown performance and key parameters of the devices are investigated by changing the position and concentration of the acceptor traps in the buffer layer. The results show that with the increase of trap concentration, the traps capture electrons and reduce the off-state leakage current, which can improve breakdown voltage of the devices. At the same time, as the trap concentration increases, the ionized traps make a high additional electric field near the drain edge, leading to the decrease of breakdown voltage. With the combined two effects above, the breakdown voltage almost ultimately saturates. When the source-to-gate (Access-S) region in the GaN buffer layer is doped alone, the minimum and most linear leakage current for the same trap concentrations are obtained, and the additional electric field has a relatively small effect on the electric field peak near the drain as the ionized traps are furthest from drain. All these factors make the breakdown voltage increase more controllably with the Access-S region doping, and it is a more potential way to improve the breakdown performance.

Quasi-normally off AlGaN/GaN high-electron-mobility transistors with p-type CuOx gate synthesized through magnetron reactive sputtering

In this study, magnetron reactive sputtering using a copper oxide target was performed to obtain a series of high-quality CuOx films with high hole concentration. The results of X-ray photoelectron spectroscopy and Hall measurements revealed that the hole concentration exhibited a negative correlation to the Cu + to Cu2+ ratio in the p-type CuOx film. This phenomenon indicated that the hole concentration can be modulated by adjusting film deposition conditions. Considering the high hole concentration and fine surface quality, these CuOx films were used as p-type gates without gate etching and positively shifted the threshold voltage (Vth) of AlGaN/GaN high-electron-mobility transistors (HEMTs). This study is the first to achieve quasi-normally off GaN HEMTs using CuOx gates, in which Vth positively shifted approximately 2.5 V and reached 0.5 V. Because of the excellent surface quality of the CuOx gate, the off-state current and gate leakage current of GaN HEMTs improved considerably. This study verified that CuOx is a promising gate candidate for fabricating low-cost, normally off AlGaN/GaN HEMTs.

Effect of strain on quantum transport in fully-hydrogenated silicene based field effect transistor

In this work, the impact of strain on the quantum transport in fully hydrogenated silicene based field effect transistor (FET) has been comprehensively studied by using the multi-scale approach consisting of density functional theory (DFT), Wannier function based tight binding and the non-equilibrium Green's Function (NEGF) formalism. It has been observed that, the buckling height of the fully hydrogenated silicene increases with the compressive strain and it reduces with the tensile strain. Therefore, the application of the strain on the fully hydrogenated silicene tunes the bandgap and for the top surface fully hydrogenated silicene it is found to be 1.34 eV. Further, it has been noticed that, in comparison to uniaxial compressively strained hydrogenated silicene, the bandgap reduction in the biaxial compressively strained hydrogenated silicene is higher. In addition to this, as compared to uniaxial tensile strained hydrogenated silicene, the increase in effective mass of the electron is more dominant in the biaxial tensile strained fully hydrogenated silicene. It has also been observed that, due to increase in compressive strain, the on-state drive current (ION) of the FET improves whereas due to reduction in bandgap, the off-state leakage current (IOFF) increases. On the other hand, the variations in the tensile strain present in the channel of the device improves the ION. Unlike the effect of variations in compressive strain on transfer characteristics, the variations in the tensile strain does not affect both sub-threshold slope and the IOFF of the device.

An Artificial Neural Network Implemented Using Parallel Dual-Gate Thin-Film Transistors

Implementing in-memory computation, an artificial neural network (ANN) consisting of thin-film transistors (TFTs) monolithically integrated in each unit of an array of capacitors is constructed. Both single-gate and parallel, dual-gate (DG) TFTs are deployed. The capacitors and the DG TFTs serve as the respective memory and computational elements. The DG TFT offers the capability of amplifying a weak but relevant input signal and suppressing a strong but irrelevant input signal across a synaptic gap, and the storage of charge on the capacitor is pseudostatic because of the exceptionally low OFF-state leakage current of the accompanying address TFT built on a metal–oxide semiconductor. The feasibility of such an ANN is demonstrated using a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4\times6$ </tex-math></inline-formula> array for classifying a specific set of Tetris patterns.

Optimisation of geometric aspect ratio of thin film transistors for low-cost flexible CMOS inverters and its practical implementation

A low-cost, flexible processor is essential to realise affordable flexible electronic systems and transform everyday objects into smart-objects. Thin film transistors (TFTs) based on metal-oxides (or organics) are ideal candidates as they can be manufactured at low processing temperatures and low-cost per unit area, unlike traditional silicon devices. The development of complementary metal–oxide–semiconductor (CMOS) technology based on these materials remains challenging due to differences in performance between n- and p-type TFTs. Existing geometric rules typically compensate the lower mobility of the metal-oxide p-type TFT by scaling up the width-to-length (W/L) ratio but fail to take into account the significant off-state leakage current. Here we propose the concept of an optimal geometric aspect ratio which maximises the inverter efficiency represented by the average switching current divided by the static currents. This universal method is especially useful for the design of low-power CMOS inverters based on metal-oxides, where the large off-current of the p-type TFT dominates the static power consumption of the inverter. We model the inverter efficiency and noise margins of metal-oxide CMOS inverters with different geometric aspect ratios and compare the performance to different inverter configurations. The modelling results are verified experimentally by fabricating CMOS inverter configurations consisting of n-type indium-silicon-oxide (ISO) TFTs and p-type tin monoxide (SnO) TFTs. Notably, our results show that reducing W/L of metal-oxide p-type TFTs increases the inverter efficiency while reducing the area compared to simply scaling up W/L inversely with mobility. We anticipate this work provides a straightforward method to geometrically optimise flexible CMOS inverters, which will remain relevant even as the performance of TFTs continues to evolve.

Vertical Gate-All-Around Device Architecture to Improve the Device Performance for Sub-5-nm Technology.

In this work, we propose a vertical gate-all-around device architecture (GAA-FinFET) with the aim of simultaneously improving device performance as well as addressing the short channel effect (SCE). The GAA-FinFET was built using the technology computer-aided design (TCAD) simulation tool, and then, its electrical characteristics were quantitatively evaluated. The electrical characteristics of the GAA-FinFET were compared to those of conventional FinFET and nano-sheet FET (NSFET) at 7 nm or 5 nm nodes. When comparing the GAA-FinFET against the FinFET, it achieved not only better SCE characteristics, but also higher on-state drive current due to its gate-all-around device structure. This helps to improve the ratio of effective drive current to off-state leakage current (i.e., Ieff/Ioff) by ~30%, resulting in an improvement in DC device performance by ~10%. When comparing the GAA-FinFET against the NSFET, it exhibited SCE characteristics that were comparable or superior thanks to its improved sub-channel leakage suppression. It turned out that the proposed GAA-FinFET (compared to conventional FinFET at the 7 nm or 5 nm nodes, or even beyond) is an attractive option for improving device performance in terms of SCE and series resistance. Furthermore, it is expected that the device structure of GAA-FinFET is very similar to that of conventional FinFET, resulting in further improvement to its electrical characteristics as a result of its gate-all-around device structure without significant modification with respect to the processing steps for conventional FinFET.

A Novel L-Gate InGaAs/GaAsSb TFET with Improved Performance and Suppressed Ambipolar Effect.

A heterojunction tunneling field effect transistor with an L-shaped gate (HJ-LTFET), which is very applicable to operate at low voltage, is proposed and studied by TCAD tools in this paper. InGaAs/GaAsSb heterojunction is applied in HJ-LTFET to enhance the ON-state current (ION). Owing to the quasi-broken gap energy band alignment of InGaAs/GaAsSb heterojunction, height and thickness of tunneling barrier are greatly reduced. However, the OFF-state leakage current (IOFF) also increases significantly due to the reduced barrier height and thickness and results in an obvious source-to-drain tunneling (SDT). In order to solve this problem, an HfO2 barrier layer is inserted between source and drain. Result shows that the insertion layer can greatly suppress the horizontal tunneling leakage appears at the source and drain interface. Other optimization studies such as work function modulation, doping concentration optimization, scaling capability, and analog/RF performance analysis are carried out, too. Finally, the HJ-LTFET with a large ION of 213 μA/μm, a steep average SS of 8.9 mV/dec, and a suppressed IOFF of 10−12 μA/μm can be obtained. Not only that, but the fT and GBP reached the maximum values of 68.3 GHz and 7.3 GHz under the condition of Vd = 0.5 V, respectively.

인공 신경망 모델을 이용한 Work Function Variation (WFV), Random Dopant Fluctuation (RDF)가 유발하는 5㎚ 노드 FinFET의 전기적 특성 변화 예측

Work function variation (WFV), Random dopant fluctuation (RDF) 현상은 FinFET에서 발생하는 Process-induced variation 현상의 주요 원인이다. 본 연구에서는 5nm 노드 FinFET에서 WFV/RDF가 유도하는 전기적 소자 특성의 변동 예측을 위해 Artificial neural network (ANN) 모델을 사용한 발전된 방법을 제안한다. 본 논문에서의 ANN 모델은 4개의 input feature [i.e., Average grain size(AGS), Source/Drain doping density(S/D doping), Retrograde channel doping concentration(RCD doping), Retrograde channel doping peak point(RCD Peak)]를 사용해서 소자 성능을 나타내는 7개 output feature [i.e., off-state leakage current(ISUBoff/SUB), saturation drain current(ISUBdsat/SUB), linear drain current(ISUBdlin/SUB), low drain current(ISUBdlo/SUB), high drain current (ISUBdhi/SUB), saturation threshold voltage(VSUBtsat/SUB) and linear threshold voltage(VSUBtlin/SUB)]를 예측한다.

Polarization modulation of 2DEG toward plasma-damage-free GaN HEMT isolation

GaN electronics have hinged on invasive isolation such as mesa etching and ion implantation to define device geometry, which, however, suffer from damages, hence potential leakage paths. In this study, we propose a new paradigm of polarization isolation utilizing intrinsic electronic properties, realizing in situ isolation during device epitaxy without the need of post-growth processing. Specifically, adjacent III- and N-polar AlGaN/GaN heterojunctions were grown simultaneously on the patterned AlN nucleation layer on c-plane sapphire substrates. The two-dimensional electron gas (2DEG) was formed at III-polar regions but completely depleted in N-polar regions, thereby isolating the 2DEG channels with a large 3.5 eV barrier. Structures of polarization-isolated high electron mobility transistors (PI-HEMTs) exhibit significantly reduced isolation leakage currents by up to nearly two orders of magnitude at 50 V voltage bias compared to the state-of-the-art results. Aside from that, a high isolation breakdown voltage of 2628 V is demonstrated for the PI-HEMT structure with 3 μm isolation spacing, which is two-times higher than a conventional mesa-isolation HEMT. Moreover, the PI-HEMT device shows a low off-state leakage current of 2 × 10−8 mA/mm with a high Ion/Ioff ratio of 109 and a nearly ideal subthreshold slope of 61 mV/dec. This work demonstrates that polarization isolation is a promising alternative toward the plasma-damage-free isolation for GaN electronics.

Silicon and Germanium Vertical Super-Thin Body (VSTB) FET: A Comparative Performance Overview Including Architectural Stress-Strain Impact

This article aims to develop a comprehensive understanding of the comparative performance of a vertical super-thin body (VSTB) FET in terms of two device material variations (silicon/Si and germanium/Ge) first time with the aid of 3D Senaturus TCAD tool. More importantly, the influence of the inevitable architectural stress (exerted over the thin body by the thick dielectric walls) on the transfer characteristic of the device is also addressed for Si/Ge device. From the perspective of suitability in high-performance circuits, Ge outperforms Si by enhancing on-state current (I on ) by 30.28, 30.29, 29.91, and 26.98 μA at channel length of 10, 20, 30, and 40 nm, respectively, with an improvable deterioration in off-state leakage current, subthreshold swing, and drain-induced-barrier-lowering. Further, a three-dimensional stress analysis reveals that stress increases I on more in Ge-device compared to its Si-counterpart. As expected, a similar nature is observed for the strain application. Finally, the radio-frequency study shows that although the relative performance of Ge with respect to Si in terms of input capacitance, gate-drain capacitance, and output conductance is inferior, the greater transconductance of Ge than Si lowers intrinsic delay and enhances the peaks of intrinsic gain, unit-gain cut-off frequency, and gain-bandwidth-product.

Effect of GaN cap layer on the performance of AlInN/GaN-based HEMTs

The effect of the GaN cap layer on the performance of AlInN/GaN-based HEMTs has been studied. Detailed analysis of the DC characteristics reveals that the addition of the GaN cap layer reduces the gate leakage current and increases the saturation drain current of HEMT. We have observed a slight increase in the two-dimensional electron gas density on the addition of the GaN cap layer. The addition of the GaN cap layer shifts the threshold voltage towards the negative direction, reduces the off-state drain leakage current, improves subthreshold swing, and enhances the ION/IOFF ratio of HEMT. The TCAD simulation shows that the addition of the GaN cap layer reduces the peak electric field at the drain side edge of the gate and improves the breakdown voltage. From the double pulsed ID-VDS measurement, we have found that the presence of the GaN cap layer reduces the current collapse due to gate-lag and drain-lag by passivating the surface traps of the access regions. Although there is a slight reduction in transconductance, the current gain cut-off frequency (fT) of the HEMT with GaN cap is higher than the HEMT without GaN cap.

A Novel S-Gate-Assisted SOI n-MOSFET for Total Ionizing Dose Radiation Reinforcement

In this article, a novel S-gate-assisted silicon-on-insulator n-channel metal–oxide–semiconductor field-effect transistor (SGA SOI n-MOSFET) structure is proposed in order to suppress the total ionizing dose (TID) effect. The new structure settles the radiation-induced leakage current by isolating both the source and drain from the shallow trench isolation (STI) oxides and introducing two auxiliary gates. This work simulates the TID irradiation of three SOI n-MOSFET devices by Sentaurus TCAD and verifies the anti-TID irradiation characteristics of the proposed SGA SOI n-MOSFET. After the novel SGA SOI n-MOSFET was irradiated with 500 krad(Si), the OFF-state leakage current is only marginally increased, the ON-state leakage current is almost unchanged, the threshold voltage drift is 9.423%, and the transconductance degradation is only 7.453%. The simulation results demonstrated the proposed SGA SOI n-MOSFET resisted TID radiation doses up to 500 krad(Si). Meanwhile, the SGA SOI n-MOSFET is much more compact and saves tremendous cost compared with the H-gate-assisted (HGA) SOI n-MOSFET during very large scale integration (VLSI) fabrication and mass production. Moreover, the SGA SOI n-MOSFET solves the disadvantages of the ring-gate-assisted (RGA) SOI n-MOSFET complex aspect ratio <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${W}/{L}$ </tex-math></inline-formula> design. The SGA SOI n-MOSFET offers a better alternative for nonultrahigh radiation dose environments.

P-GaN field plate for low leakage current in lateral GaN Schottky barrier diodes

High-voltage gallium nitride Schottky barrier diodes (SBDs) suffer from large off-state leakage current, which further degrades during operation at high temperatures and limits the device blocking capabilities. The key to achieving low off-state leakage is to protect the Schottky barrier from the high electric field, which is challenging by employing conventional field plate structures due to their large pinch-off voltage. In this work, we propose a simple AlGaN/GaN SBD architecture based on a p-GaN cap layer to achieve excellent off-state performance with a very low leakage current. By properly designing the AlGaN barrier and p-GaN cap, the pinch off-voltage of the p-GaN field plate is carefully controlled and the voltage drop over the Schottky junction is effectively reduced. In addition, a large carrier concentration in the access region is achieved, leading to a reduced sheet resistance. This results in good on-state performance along with a very low leakage current of ∼1 nA/mm at 400 V, which is maintained well below 100 nA/mm up to elevated temperatures of 150 °C. Moreover, the proposed architecture shares the well-established fabrication process of commercial p-GaN HEMTs and, thus, represents a promising and viable solution for future GaN diodes.

Toward Monolithically Integrated Hybrid CMOS-NEM Circuits

Nanoelectromechanical (NEM) switches offer the advantages of zero OFF-state leakage current, abrupt switching characteristics, nonvolatile (NV) operation, and relatively low ON-state resistance as compared with CMOS transistors predominantly used for digital computing today. NEM switches can be implemented using metallic interconnect layers formed in the back-end-of-line (BEOL) steps of a standard CMOS IC manufacturing process, in order to enable compact implementation of hybrid CMOS-NEM circuits. In this article, a release-etch method is developed for realizing BEOL NV-NEM switches with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\leq 100$ </tex-math></inline-formula> -nm contact gaps. A functional array of BEOL NV-NEM switches is used to implement a hybrid CMOS-NEM IC for data search applications. NV-NEM switch design optimization to minimize the programming voltage and accelerate switching speed is discussed. A scaled NV-NEM technology is projected to be advantageous for high-speed, low-power reconfigurable computing applications. This projection is validated with experimental data for a BEOL NV-NEM switch implemented with a conventional 16-nm CMOS IC manufacturing process.

32 × 32 Pixelated High-Power Flip-Chip Blue Micro-LED-on-HFET Arrays for Submarine Optical Communication.

This work proposes the use of integrated high-power InGaN/GaN multiple-quantum-well flip-chip blue micro light-emitting diode (μ-LED) arrays on an AlGaN/GaN-based heterojunction field-effect transistor (HFET), also known as a high electron mobility transistor (HEMT), for various applications: underwater wireless optical communication (UWOC) and smart lighting. Therefore, we demonstrate high-power μ-LED-on-HEMT arrays that consist of 32 × 32 pixelated μ-LED arrays and 32 × 32 pixelated HEMT arrays and that are interconnected by a solder bump bonding technique. Each pixel of the μ-LED arrays emits light in the HEMT on-state. The threshold voltage, the off-state leakage current, and the drain current of the HEMT arrays are −4.6 V, <~1.1 × 10−9 A at gate-to-source voltage (VGS) = −10 V, and 21 mA at VGS = 4 V, respectively. At 12 mA, the forward voltage and the light output power (LOP) of μ-LED arrays are ~4.05 V and ~3.5 mW, respectively. The LOP of the integrated μ-LED-on-HEMT arrays increases from 0 to ~4 mW as the VGS increases from −6 to 4 V at VDD = 10 V. Each pixel of the integrated μ-LEDs exhibits a modulated high LOP at a peak wavelength of ~450 nm, showing their potential as candidates for use in UWOC.