Off-state Current Research Articles

Reduction of off-state drain current in AlN/[formula omitted] HEMT by trap state engineering

In this work, we report various strategies to reduce the off-state drain leakage current (IOFF) in AlN/β−Ga2O3 high electron mobility transistor (HEMT) by 2D device simulation. We have investigated the effect of access region, channel doping concentration, barrier layer thickness, and trap state engineering on IOFF. The formation of a parallel channel deep into the substrate has been found to be responsible for large IOFF. All other strategies except trap state engineering have an incremental effect on IOFF. However, the device’s IOFF was reduced by around 12 orders of magnitude by trap-state engineering. Simultaneously, the on-state performance was unaffected, resulting in an elevated ION/IOFF current ratio of (1013). A steep subthreshold slope of 0.267 (V/dec) was also obtained. Further, we have investigated the impact of both donor- and acceptor-type traps on subthreshold characteristics. These promising results highlight the potential of AlN/β−Ga2O3 HEMT as a switch and for future high-power nanoelectronics applications.

Barium titanate write-once read-many times resistive memory with an ultra-high on/off current ratio of 108

Write-once read-many times (WORM) resistive memories fabricated using perovskite barium titanate (BaTiO3, BTO) resistive switching (RS) layer are demonstrated in this study. The BTO RS layers with thicknesses of 3.2–8.5 nm are fabricated by radio frequency sputtering at room temperature. Annealing processes at 400–600 °C are used to modify the oxygen vacancy content in the BTO layer and thereby control the OFF-state current of an Al/BTO/n+-Si WORM device. The ION/IOFF ratio increases with increasing annealing temperature until 500 °C. A negative effect is observed when the temperature further rises to 600 °C. The optimal Al/BTO/n+-Si device shows an ultra-high ION/IOFF ratio of 108 and a low coefficient of variation of 6% for set voltages. The writing speed is 80 ns and the power consumption is 400 pJ. In addition, retention and stress tests are performed to confirm high data storage reliability of the device. Mechanisms for voltage-polarity independent writing process and the related energy band diagrams are explored.

Integration of low-thermal-budget In2O3 NMOS inverter and GaN HEMT for power electronics

Herein, we demonstrated an “interposer”-style integration of In2O3 FET-based gate-driver circuitry wire bonded to an AlGaN/GaN high electron mobility transistor (HEMT) device grown on a GaN-on-Si substrate, and its feasibility for power electronics was discussed. The normally-on AlGaN/GaN HEMT exhibited a threshold voltage of −2.8 V, with a maximum drain current density of 265 mA/mm. The device also showed good off-state performance, such as a high ON/OFF ratio (Ion/Ioff) of ∼1010 with a breakdown voltage of ∼445 V and an off-state leakage current of ∼10−12 A. The low-temperature processed In2O3 driver circuitry exhibited a high gain of ∼64 and a maximum operating frequency of 2 kHz. The temperature-dependent study of the voltage transfer characteristics (VTC) of In2O3 driver circuitry exhibited stable operation up to 125 °C. An integrated In2O3 driver circuitry with GaN HEMT was demonstrated, marked by a 50 mA/mm drain current for circuit response of one cycle during the ON state. These results pave the way for future monolithic integration of oxide semiconductor-based gate-driver circuitry with power switches for energy-efficient integrated circuits.

Assessment of temperature and ITCs on single gate L-shaped tunnel FET for low power high frequency application

In a vertical TFET structure, controllability over the gate is enhanced because of the favorable electrostatic potential and tunneling under the entire gate region by preventing the direct source to drain tunneling. For an L-shaped TFET, the Band-to-Band-Tunneling (BTBT) is perpendicular and parallel to the channel length. Also, it has a higher I on (ON-current) with suppressed ambipolar current (low I ambi ) and is more scalable than other vertical BTBT mechanism-based TFET structures. The reliability of n-type single gate L-shaped TFET (SG-nLTFET) is investigated by examining: (1) impact of temperature (Temp K ) variation (from 260 K to 460 K) and (2) Interface trap charge (ITCs) polarity at fixed charge density on analog /RF /linearity figure of merits (FOMs). The obtained results reveal that change in polarity of ITCs at the Si/HfO 2 interface,modifies the analogue characteristics of the SG-nLTFET significantly in terms of turn-on voltage as well as I on . The temperature sensitivity of SG-nLTFET device indicates that the ShockleyReadHall (SRH) and Trap-Assisted-Tunneling (TAT) phenomenon dominates at lower gate bias and degrades the I on /I off ratio at high temperatures. On the other hand, the BTBT mechanism predominates in the subthreshold regime of transfer characteristics. Furthermore, the results reveal that the off-state current (I off ) degrades dramatically at high temperatures. According to the empirical analysis, SG-nLTFET is insusceptible to Positive-ITCs (Donor trap charges, P-ITCs) present at Si/HfO 2 interface in comparison to Negative-ITCs (Acceptor trap charges, N-ITCs).

Composite channel 100 nm InP HEMT with ultrathin barrier for millimetre wave applications

This study introduces a High Electron Mobility Transistor (HEMT) designed for millimeter-wave applications, utilizing a composite channel structure based on InP and InGaAs-InAs-InGaAs. The proposed device incorporates an ultra-thin 2 nm barsrier layer, a distinctive composite channel topology, and a judicious selection of III-V materials. These features collectively contribute to an improved confinement of electrons within the channel, thereby improving the concentration of two-dimensional electron gas (2DEG), and consequently, enhancing the mobility and speed of the device. The proposed device exhibits a unity current gain frequency (f T) of 249 GHz and a maximum oscillation frequency (f MAX) of 523.9 GHz, accompanied by a current gain of 67.7 dB at 0.1 GHz. The off-state leakage current is maintained within the nanoampere range, and the minimum noise figure (NF MIN) is merely 0.76 dB at 10 GHz. A comparative analysis of DC and RF performance, along with an examination of associated parasitic elements, is conducted among various composite channel HEMTs proposed in recent literature. A quantitative justification is provided for the superiority of InGaAs-InAs-InGaAs channel HEMTs, establishing their heightened f T and f MAX. The proposed InGaAs-InAs-InGaAs channel HEMTs exhibit 1.4 times improved f T and f MAX, coupled with only half the NF MIN in comparison to their InGaAs-InP-InGaAs channel counterparts. To further comprehend the device’s behavior under varying RF conditions, a frequency-dependent intrinsic Field-Effect Transistor (FET) model is presented. This model facilitates the analysis of the device’s performance and allows the identification of the impact of individual parameters on the overall system.

Effect of ambipolarity suppression in PNPN TFET with dopant segregated Schottky-drain technique

In this paper, a comparative analysis of ambipolarity suppression in conventional PNPN-TFET(D-1) is studied using TCAD simulation. By replacing the drain with metal silicide, and by implementing the dopant-segregated Schottky-barrier drain (DSSBD) in conventional PNPN-TFET, two new devices named PNPM-TFET(D-2) and DSSB-PNPM-TFET(D-3) has been proposed for suppressing the ambipolarity. The narrow n+ doped pocket between the Metallic drain and Si-Channel is essentially a DSSDB technique. Compared with the D-1, the proposed D-2 suppresses the ambipolarity by a factor of 994.92 and the proposed D-3 by a factor of 7.23 × 106. In addition, along with the abovementioned reduced ambipolarity, the DSSB in D-3 also much improves the OFF-state current, thus ION/IOFF ratio for D-3 also improved by a factor of 8.42 than D-1. The DSSB technique suppresses the ambipolarity in D-3 with almost unchanged ON current. Therefore, the benefit of improved ON current due to the source-pocketing architecture of the PNPN in the D-3 remains as it is.

Processes to enable hysteresis-free operation of ultrathin ALD Te p-channel field-effect transistors.

Recently, tellurium (Te) has been proposed as a promising p-type material; however, even the state-of-the-art results couldn't overcome the critical roadblocks for its practical applications, such as large I-V hysteresis and high off-state leakage current. We developed a novel Te atomic layer deposition (ALD) process combined with a TeOx seed layer and Al2O3 passivation to detour the limitations of p-type Te semiconducting materials. Also, we have identified the origins of high hysteresis and off current using the 77 K operation study and passivation process optimization. As a result, a p-type Te field-effect transistor exhibits less than 23 mV hysteresis and a high field-effect mobility of 33 cm2 V-1 s-1 after proper channel thickness modulation and passivation. Also, an ultralow off-current of approximately 1 × 10-14 A, high on/off ratios in the order of 108, and a steep slope subthreshold swing of 79 mV dec-1 could be achieved at 77 K. These enhancements strongly indicate that the previously reported high off-state current was originated from interfacial defects formed at the metal-Te contact interface. Although further studies concerning this interface are still necessary, the findings herein demonstrate that the major obstacles hindering the use of Te for ultrathin p-channel device applications can be eliminated by proper process optimization.

Impact of Nanowire Radius and Channel Thickness with High-k Gate Dielectric in GAA-JLT

As the transistor’s size becomes smaller, degradation in the short-channel effects (SCEs) becomes more apparent. This leads to research work on multi-gate transistors such as the Fin-Field Effect Transistor (FinFET) and Gate-All-Around (GAA) transistor, where the 3D architecture have been shown to have superior performance as compared to conventional planar transistor. Transistor without junctions (JLT) which realizes a single type of doping has also been gaining popularity for biosensor applications due to its superior electrostatic performances in terms of Drain-Induced Barrier Lowering (DIBL), off-state leakage current (Ioff) and Subthreshold Slope (SS). In this work, the impact of changes in parameters such as the gate oxide material, nanowire radius and channel thickness toward the performance of a Gate-all-around JLT (GAA-JLT) have been studied using TCAD simulator. It was found that smaller nanowire radius and thicker channel produces lower DIBL, Ioff and SS, with the use of HfO2 as gate oxide materials shows better results than Si3N4. Meanwhile, the impact of parameters variations seemed to be negligible on the on-state current (Ion). The outcome of this work can be used as a basis to understand the impact of structural parameters variations towards the performance of a more complex GAA-JLT structure.

Estimation of electrostatic, analogue, Linearity/RF figures-of-merit for GaN/SiC HEMT

An experimental examination of AlGaN/GaN/SiC HEMT multi-bias behaviour is presented in this paper to add to the enormous amount of device performance data in varied operating bias conditions. The study investigates various device parameters, including electrostatic performance, DC figures of merit, RF figures of merit and non-linear parameters under multi-bias conditions. The electrostatic performance is evaluated by analyzing the Ids-Vds transfer curves, ON-state and OFF-state currents, subthreshold slope and subthreshold swing. The output current, transconductance (gm), 2nd-and 3rd-order transconductance (gm2, and gm3) behaviour of the GaN device over multi-bias indicates a significant potential. The transconductance-reliant non-linear performance is assessed by analyzing voltage intercept points (VIP2 and VIP3), 3rd-order intercept point (IIP3), 1-dB compression point (1-dB CP), 3rd-order intermodulation distortion (IMD3), and total harmonic distortion (THD). In the case of RF parameters, the maximum ft and fmax values are 41 GHz and 125.7 GHz, respectively, and GBW up to 640 GHz was achieved. The relevant parameters, specifically the gain frequency product (GFP), transconductance frequency product (TFP), and the gain transconductance frequency product (GTFP), demonstrated remarkable results with maximum values of 683 GHz, 380.1 GHz/V, and 9827.7 GHz/V, respectively. These findings provide some valuable perceptions which would facilitate the fabrication of cutting-edge technologies for present and future applications.

Demonstration of a novel Dual-Source Elevated-Channel Dopingless TFET with improved DC and Analog/RF performance

In this paper, a novel Dual-Source Elevated-Channel Dopingless TFET (DSEC-DLTFET) is proposed to enhance the dc and analog/high-frequency (HF) performance of the device. TCAD-based simulation results reveal that an additional source region of the proposed device improves the ON-state current by enhancing the rate of charge carriers tunneling into the channel during ON-state while the elevated channel induces a barrier for the charge carriers tunneling during OFF-state, thereby reducing the leakage current in the device. The improvement in the ON- and OFF-state currents is found to be an order of ∼2 and ∼3 as compared with the conventional DLTFET. Furthermore, to eliminate the trade-off between the ambipolarity and ON-state current, drain metal engineering (DE) is employed to the proposed device where in the drain metal, which is mainly responsible for the creation of electron plasma in the drain region, is composed of two different work functions. The higher work function metal near to the channel-drain interface enhances the barrier width, thus restricting the tunneling rate of charge carriers during the negative gate bias i.e. ambipolar state. Moreover, DE-DSEC shows the improvement in HF performances owing to reduction in the parasitic capacitances. Due to the improved DC and analog/HF performances, transient response of DE-DSEC based n-TFET inverter is also found to be better than that of the conventional DLTFET.

Improving the selector characteristics of ovonic threshold switch via UV treatment process

In this study, we investigated the influence of ultraviolet (UV) treatment on the ovonic threshold switch (OTS) to improve its selector properties. Our findings demonstrate that iteratively applying UV treatment during the film deposition phase considerably improves device characteristics compared to a single UV treatment. Consequently, this process provided a significant decrease in the forming voltage, maintaining outstanding switching features, with an off-state current of approximately 2 nA. Furthermore, the refined UV treatment process resulted in an impressive 45% improvement in threshold voltage drift characteristics and facilitated excellent switching uniformity. X-ray photoelectron spectroscopy analysis revealed alterations in the bonding structure of the Si–Te–As–Ge film after UV exposure. Specifically, a transition was observed from unstable homopolar bonds, such as As-As or Te–Te, to their more stable heteropolar equivalents, such as As–Te. These results highlight the potential of UV treatment as an effective method for enhancing the OTS performance.

Atomic and electronic origin of robust off-state insulation properties in Al-rich AlxTey glass for ovonic threshold switching applications

Ovonic threshold switching (OTS) selectors play a critical role in suppressing the sneak-path current of three-dimensional crossbar integration circuits. Compared to conventional nonmetal-telluride OTS selectors, selectors based on AlxTey glass are found to have both satisfactory on-state current and selectivity. However, it is unclear why the Al-rich AlxTey glass-based OTS selectors have robust insulation properties for reducing the off-state current. This work reveals the structure–property correlations of amorphous AlxTey at the atomic scale by first-principles calculations. It is found that the stoichiometric Al2Te3 glass tends to have a clean bandgap owing to the covalent and dative bonds formed by non-equivalent sp3-hybridized Al orbitals and the lone-pair electrons of Te. Unexpectedly, for Al-rich AlxTey glass (Al2.21Te2.79), the Al–Al bonds formed by redundant Al-atoms have an integrated crystal orbital bond index (ICOBI) of 0.8–0.9, which is much larger than that of Al–Al bonds in pure metals (0.227), indicating they are covalent. It is the covalent Al–Al bonds that ensure the robust insulation characteristics of Al-rich AlxTey glass, while the Te–Te interaction in the Al-poor AlxTey glass (Al1.79Te3.21) produces midgap states, thereby reducing the insulativity. The presented atomic and electronic pictures here will provide useful theoretical insights for designing OTS selectors with improved performances.

Insights into the impact of random dopant fluctuation on ferroelectric germanium source vertical TFET

This paper investigates the effect of random dopant fluctuation (RDF) on the performance of ferroelectric Germanium source vertical tunnel field effect transistor (FE GeS-vTFET) using 3-D device simulation. The variation in the on-state current (σION), off-state leakage current (σIOFF), current ratio σ(ION/IOFF), subthreshold swing (σSS), threshold voltage (σVTH), total gate capacitance (σCgg), transconductance (σgm) and cut-off frequency (σfT) for different source doping concentration and source thickness due to the effect of RDF are evaluated. The findings indicate an increasing tendency in RDF with higher doping concentration in the source region. The variation in the on-current is from 0.2173 mA to 0.2337 mA (∼1.075 times higher), and σIOFF varies from 4.939 fA to 16.545 fA (∼3.349 times higher) from 1 × 1020 /cm3 to 3 × 1020 /cm3 doping concentration, respectively for Germanium source thickness of 12 nm. RDF within the source region mainly contributes to the threshold voltage variation of about 92 % in all regions. The randomized dopant-induced σVTH for the FE GeS-vTFET compared with other field effect transistors of the same technology node showed a substantial reduction in σVTH, signifying that the device is more immune to the effects of RDF. Furthermore, the effect of temperature on the switching properties of the FE GeS-vTFET has been studied.

A High-Performance InGaAs Vertical Electron-Hole Bilayer Tunnel Field Effect Transistor with P+-Pocket and InAlAs-Block.

To give consideration to both chip density and device performance, an In0.53Ga0.47As vertical electron-hole bilayer tunnel field effect transistor (EHBTFET) with a P+-pocket and an In0.52Al0.48As-block (VPB-EHBTFET) is introduced and systematically studied by TCAD simulation. The introduction of the P+-pocket can reduce the line tunneling distance, thereby enhancing the on-state current. This can also effectively address the challenge of forming a hole inversion layer in an undoped InGaAs channel during device fabrication. Moreover, the point tunneling can be significantly suppressed by the In0.52Al0.48As-block, resulting in a substantial decrease in the off-state current. By optimizing the width and doping concentration of the P+-pocket as well as the length and width of the In0.52Al0.48As-block, VPB-EHBTFET can obtain an off-state current of 1.83 × 10-19 A/μm, on-state current of 1.04 × 10-4 A/μm, and an average subthreshold swing of 5.5 mV/dec. Compared with traditional InGaAs vertical EHBTFET, the proposed VPB-EHBTFET has a three orders of magnitude decrease in the off-state current, about six times increase in the on-state current, 81.8% reduction in the average subthreshold swing, and stronger inhibitory ability on the drain-induced barrier-lowering effect (7.5 mV/V); these benefits enhance the practical application of EHBTFETs.

Performance improvement of α-6T thin film sensors based on F16CuPc buffer layer

A F16CuPc buffer layer is proposed to be added to improve the performance of the sensors. The change of relative responsivity of sensors with and without buffer layer was investigated. The relative responsivity of sensors with buffer layer reached 448.32 % from the off-state current of transistors under 20 ppm NO2 gas. The result was 51.45 % higher than that of the sensors without buffer layer. The sensitivity for NO2 gas reaches 2087.92 %/ppm, which is 25.80 % higher than the sensors without buffer layer. The addition of buffer layer is beneficial for the transmission of charge carriers. Therefore, it is possible to obtain highly responsive sensors, which provide a feasible solution for the study of high-performance organic thin film sensors.

Enhancing Gating Performance in Organic Molecular Field-Effect Transistors by Introducing Polar Azulene Components.

Organic molecular field-effect transistors (FETs) are promising building components for future electronic circuits. Efficient control of charge transport properties is one key issue in the design of organic molecular FETs. In this study, we propose a redesign of a naphthalene-based FET by introducing two azulene components in opposite dipole moment directions. Using density functional theory combined with non-equilibrium Green's function, the simulated electronic transport characteristics reveal that the introduction of polar azulene components effectively narrows the frontier molecular orbitals gap, leading to an increase in the ON-state current. Meanwhile, the OFF-state current is significantly suppressed by highly localizing the dominant electronic transport channel. As a result, improved gate controllability is achieved with a higher ON-OFF current ratio, which is nearly seven times higher than that of the naphthalene-based FET device. These findings provide theoretical directions for future design of organic molecular FET devices with enhanced gating regulation efficiency.

Supramolecular Transistors with Quantum Interference Effect.

The charge transport through supramolecular junctions exhibits unique quantum interference (QI) effects, which provide an opportunity for the design of supramolecular transistors. Benefiting from the configuration dependence of QI, configuration control of the supramolecular assemblies to demonstrate the QI features is a key but challenging step. In this work, we fabricated the supramolecular transistors and investigated the charge transport through the conducting channel of the individual π-stacked thiophene/phenylene co-oligomers (TPCOs) using the electrochemically gated scanning tunneling microscope break junction technique. We controlled the configuration of the supramolecular channel and switched the QI features between the anti-resonance and resonance states of the supramolecular channels. We observed the supramolecular transistor with its on/off ratio above 103 (∼1300), a high gating efficiency of ∼165 mV/dec, a low off-state leakage current of ∼30 pA, and the channel length scaled down to <2.0 nm. Density functional theory calculations suggested that the QI features in π-stacked TPCOs vary depending on the supramolecular architecture and can be manipulated efficiently by fine-tuning the supramolecular configurations. This work reveals the potential of the supramolecular channels for molecular electronics and provides a fundamental understanding of intermolecular charge transport.

Highly uniform resistive switching characteristics of KGM resistive memory through air plasma technology

In this study, a highly stable resistive switching behavior was obtained by utilizing konjac glucomannan, a biomaterial, as a dielectric layer through a solution-based process, and the ITO bottom electrode was modified by using an air plasma technique. Electrical results showed that the pretreatment device did not observe significant switching characteristics (∼101). The device, which underwent additional plasma treatment, was recognized for its significant improvements in this area, demonstrating a reduced set voltage (Vset = 0.37 V) with a 6% coefficient of variation, more than 200 consecutive cycles, and up to 90% electrical yield. Moreover, the treated device exhibited a dramatically higher memory window (&amp;gt;104) due to the relatively low off-state current. According to the XPS and UPS analysis, the work function increased from an untreated 4.3 to 5.79 eV as the treatment time increased to 180 s. The conductive filaments, which stemmed from oxygen vacancies, were introduced through plasma treatment to enhance the proportion of oxygen vacancies in the ITO films, thereby creating a stable and consistent filament path. Consequently, the systematic and reproducible resistive switching phenomenon was intensified. The reported results confirmed that the reliability and uniformity in bioelectronic devices can be accomplished through a simple and effective plasma technique. This approach paved the way for alternative applications of these devices.

Realizing On/Off Ratios over 104 for Sub-2 nm Vertical Transistors.

Vertical transistors hold promise for the development of ultrascaled transistors. However, their on/off ratios are limited by a strong source-drain tunneling current in the off state, particularly for vertical devices with a sub-5 nm channel length. Here, we report an approach for suppressing the off-state tunneling current by designing the barrier height via a van der Waals metal contact. Via lamination of the Pt electrode on a MoS2 vertical transistor, a high Schottky barrier is observed due to their large work function difference, thus suppressing direct tunneling currents. Meanwhile, this "low-energy" lamination process ensures an optimized metal/MoS2 interface with minimized interface states and defects. Together, the highest on/off ratios of 5 × 105 and 104 are realized in vertical transistors with 5 and 2 nm channel lengths, respectively. Our work not only pushes the on/off ratio limit of vertical transistors but also provides a general rule for reducing short-channel effects in ultrascaled devices.

Floating gate photo-memory devices based on van der Waals heterostructures for neuromorphic image recognition

Two-dimensional (2D) materials with reconfigurable properties show potential in neuromorphic hardware applications. However, most 2D materials-based neuromorphic hardware is volatile, which needs large energy to accomplish perception functions. Here, we report on nonvolatile floating gate photo-memory devices based on ReS2/h-BN/SnS2 van der Waals heterostructures. The devices exhibit a large memory window of ∼60 V, a high program/erase current ratio of ∼107 with excellent retention characteristics, a low off-state current of 7.4 × 10−13 A, and a high detectivity of 1.98 × 1013 cm Hz1/2 W−1, allowing for multi-bit information storage. For the multi-level storage capacity, 27 photo-memory states are obtained by pulsed laser illumination. Moreover, a neuromorphic computing network is also constructed based on the photo-memory devices with a maximum recognition accuracy of up to 90%. This work paves the way for miniaturization and high-density integration of future optoelectronics for neuromorphic hardware applications.