Demonstration of a novel Dual-Source Elevated-Channel Dopingless TFET with improved DC and Analog/RF performance

Abstract

In this paper, a novel Dual-Source Elevated-Channel Dopingless TFET (DSEC-DLTFET) is proposed to enhance the dc and analog/high-frequency (HF) performance of the device. TCAD-based simulation results reveal that an additional source region of the proposed device improves the ON-state current by enhancing the rate of charge carriers tunneling into the channel during ON-state while the elevated channel induces a barrier for the charge carriers tunneling during OFF-state, thereby reducing the leakage current in the device. The improvement in the ON- and OFF-state currents is found to be an order of ∼2 and ∼3 as compared with the conventional DLTFET. Furthermore, to eliminate the trade-off between the ambipolarity and ON-state current, drain metal engineering (DE) is employed to the proposed device where in the drain metal, which is mainly responsible for the creation of electron plasma in the drain region, is composed of two different work functions. The higher work function metal near to the channel-drain interface enhances the barrier width, thus restricting the tunneling rate of charge carriers during the negative gate bias i.e. ambipolar state. Moreover, DE-DSEC shows the improvement in HF performances owing to reduction in the parasitic capacitances. Due to the improved DC and analog/HF performances, transient response of DE-DSEC based n-TFET inverter is also found to be better than that of the conventional DLTFET.