Off-cut Angle Research Articles

(Invited) Controlling Materials Defects for SiC Power Devices

It has long been recognized that SiC power devices have the potential to outperform their Si counterparts. The superior material properties of SiC for power devices include a 3X larger bandgap, a 10X higher breakdown field and a 3X higher thermal conductivity. With these properties it is possible to design power systems that are smaller, lighter, operate at higher switching frequency and require less cooling. The growth of commercially available SiC devices is due in large part to the reduction of materials defects that has occurred over the last decade or more. Further market penetration will depend on continued materials improvements and improved techniques for identifying materials defects that degrade the yield, performance and reliability of SiC power devices. The understanding and reduction of basal plane dislocations (BPDs) have been major research efforts to improve SiC technology. BPDs cause degradation in a number of power devices including PiN diodes, BJTs and MOSFETs (1-5). While there have been dramatic improvements in reducing the BPD concentration in epitaxial layers, further improvements are still needed. The problems are more pronounced for higher voltage parts that require thicker epitaxy. Until recently, the dominant source of BPDs in epitaxial layers has been from BPDs that propagate from the substrate into the epitaxial layers. A large reduction occurred a decade ago when the wafer offcut angle was changed from 8° to 4°, which strongly increased the tendency of BPDs to convert to threading edge dislocations at the beginning of the epitaxial growth (6). The reduction of BPDs in substrates has also been important (7). Optimizing the epitaxial growth has increased the conversion efficiency at the onset of growth and in many cases can produce a drift layer that is free of BPDs over almost all of the wafer area. As the concentration of BPDs propagating from the substrate has plummeted, other sources of BPDs in the epitaxial layers have become important (8,9). One of these new sources of BPDs is the combination of implantation and activation anneal (10,11). As with all of the alternate BPD sources, these BPDs are just as degrading as BPDs coming from the substrate and must be similarly suppressed. However they originate from the top of the epitaxial layer and drift towards the substrate as well as laterally during the high temperature anneal. This formation of BPDs appears to be sensitive to the details of the implantation and activation anneal. If the penetration of SiC devices into the power electronics applications is to continue, the work to suppress BPDs as well as all other device degrading extended defects must continue. Furthermore, the techniques for quantifying their concentration in wafers that have been recently developed must become a routine part of SiC fabrication monitoring. 1. H. Lendenmann, F. Dahlquist, J. P. Bergman, H. Bleichner and C. Hallin: Mater. Sci. Forum Vol. 389-393 (2002), p. 1259. 2. R.E. Stahlbush, M. Fatemi, J.B. Fedison, S.D. Arthur, L.B. Rowland and S. Wang: J. Elec. Mater. Vol. 31 (2002), p. 370. 3. A. Agarwal, S. Krishnaswami, J. Richmond, C. Capell, S.-H. Ryu, J. Palmour, B. Geil, D. Katsis, C. Scozzie and R.E. Stahlbush: Mater. Sci. Forum Vol. 527-529 (2002), p. 1409. 4. Q. Zhang, A. Agarwal, A. Burk, M. O¢Loughlin, J. Palmour, R. Stahlbush and C. Scozzie: Mater. Sci. Forum, Vol. 645-648 (2010), p. 331. 5. A. Agarwal, H. Fatima, S. Haney and S.-H. Ryu: IEEE Elec. Dev. Lett. Vol. 28 (2007), p. 587. 6. R.L. Myers-Ward, B.L. VanMil, R.E. Stahlbush, S.L. Katz, J.M. McCrate, S.A. Kitt, C.R. Eddy, Jr., and D.K. Gaskill: Mater. Sci. Forum Vol. 615-617 (2009), p. 105. 7. M. Dudley, N. Zhang, Y. Zhang, B. Raghothamachar, S. Byrappa, G. Choi, E.K. Sanchez, D. Hansen, R. Drachev, and M.J. Loboda, Mater. Sci. Forum 645-648, 291 (2010). 8. N.A. Mahadik, R.E. Stahlbush, M.G. Ancona, E.A. Imhoff, K.D. Hobart, R.L. Myers-Ward, C.R. Eddy, D.K. Gaskill, and F.J. Kub, Appl. Phys. Lett. 100, 042102 (2012). 9. R.E. Stahlbush, N.A. Mahadik, M.J. O’Loughlin, Mater. Sci. Forum 778-780,309 (2014). 10. C. Ota, J. Nishio, K. Takao, T. Shinohe, Mater. Sci. Forum 778-780, 851 (2014). 11. R.E. Stahlbush, N.A. Mahadik, Q.J. Zhang, A.A. Burk, B.A. Hull and J. Young, Mater. Sci. Forum 821-823, 851 (2015).

Optimization of metamorphic buffers for MBE growth of high quality AlInSb/InSb quantum structures: Suppression of hillock formation

The optimization of metamorphic buffers for InSb/AlInSb QWs grown on GaAs (001) substrates is presented. With increasing surface offcut angle towards [11¯0] direction, the interaction of spiral growth around threading dislocations (TDs) with the offcut-induced atomic steps leads to a gradual change in the morphology of the AlSb buffer from one dominated by hillocks to that exhibiting near-parallel steps, and finally to a surface with increasing number of localized depressions. With the growth conditions used, the smoothest AlSb surface morphology was obtained for the offcut angles range of 0.8–1.3°. On substrates with 0° offcut, subsequent 3 repeats of Al0.24In0.76Sb/Al0.12In0.88Sb interlayers reduces the TD density of AlSb buffer by a factor of 10, while 70 times reduction in the surface density of TD-related hillocks is observed. The remaining hillocks have rectangular footprint and small facet angles with respect to GaAs (001) surface: 0.4° towards [11¯0] direction and 0.7° towards [110] direction. Their triangular-shaped sidewalls with regularly spaced atomic steps show occasional extra step insertion sites, characteristic of TD outcrops. Many of the observed sidewalls are dislocation free and offer atomically smooth areas of up to 1μm2, already suitable for high-quality InSb growth and subsequent top-down fabrication of InSb nanowires. It is proposed that the sidewalls of the remaining hillocks offer local vicinal surfaces with atomic step density optimal for suppression of TD-induced spiral growth, thus providing the important information on the exact substrate offcut needed to achieve large hillock-free and atomically smooth areas on AlInSb metamorphic buffers.

Effect of off-cut angle of hydrogen-terminated diamond(111) substrate on the quality of AlN towards high-density AlN/diamond(111) interface hole channel

Single-crystal AlN/diamond heterojunction with high-density interface hole channel is successfully obtained by metal-organic vapor phase epitaxy. The AlN layer is epitaxially grown on hydrogen-terminated (H-)diamond(111) substrate. The thermal treatment of diamond substrate just before AlN growth under hydrogen and ammonia mixture environment at 1250 °C leads to surface sheet hole density as high as ∼1.0 × 1014 cm−2 without structural reconstruction of diamond surface. In addition, the use of smaller off-cut angle (0.20 ± 0.25°) H-diamond(111) substrate combined with this treatment enables to obtain single-crystal epitaxial AlN layer, which simultaneously acts as passivation of the surface hole channel with such a high density. The AlN/H-diamond(111) heterojunction reveals type-II staggered energy band configuration with valence band offset of ∼2.0 eV, which is suitable for the fabrication of p-channel field-effect transistor using AlN-gate-insulator/diamond heterojunction. These results are promising for the development of AlN/diamond hybrid power electronic devices.

Surface morphology and optical properties of InGaN/GaN multiple quantum wells grown on freestanding GaN (0001) substrates

Surface morphology and optical properties of InGaN-based multiple quantum wells grown on c-plane freestanding GaN substrates by metalorganic vapor phase epitaxy was investigated. The surface shows a dependence on the substrate crystallographic orientation, presenting wavy and mirror-like feature with the substrate off-cut towards the [112¯0] direction and the [11¯00] direction, respectively. To get sharp hetero-interfaces, InGaN multiple-quantum-wells-based blue laser diode wafers were grown on substrates with off-cut towards the [11¯00] direction. The photoluminescence peak wavelength of the blue laser wafers shows a linearly blue shift as the substrate off-cut angle increases. A minimum spectra line width of 90 meV@450 nm can be obtained with a substrate off-cut angle of about 0.5°. These surface and optical properties were ascribed to the step growth kinetics of the wurtzite type materials.

Building III-V Devices onto Large Si Wafers

III-V semiconductor materials have been drawing extensive interests in the past decades due to their superior electronic and optical properties with great potential to improve the device performance. Compared to Si, III-V materials have mobility about 10 times higher and injection speed 2~3 times faster. CMOS devices can benefit from higher mobility and injection speed to improve operation frequency, current, power consumption, and reduce short channel effect, etc. With direct bandgap and sophisticated bandgap engineering, III-V materials also provide board range of optical applications such as optical transceivers, infrared and visible LEDs/photo detectors, photovoltaics, and lasers. It’s ideal and cost effective to integrate III-V with large Si substrate (e.g. 300mm) to take advantage of the main stream Si process flow in the semiconductor industry. The biggest challenges are lattice mismatch and anti-phase boundary (APB) caused by polar/nonpolar planes. In this paper, we reviewed the issues for growth on blanket wafers and selective growth on patterned wafers using the Applied Materials’ 300mm III-V metal-organic chemical vapor deposition tool (MOCVD). On nominal non-offcut Si (100) blanket wafers prevalently used in industry, multiple layers are typically used as buffer stack to bridge the lattice mismatch between the Si substrate and final device layer. Ge buffer layer was first tested to achieve high quality GaAs film with APB free top surface on Si substrates with very small off-cut angles (≤0.5º) [1]. For growth directly on Si, it is critical to form proper double-step Si layers prior to the III-V layer deposition to reduce APB density. We found the oxygen and carbon residual contamination is directly correlated to the APB density for GaAs growth on Si (100). The APB density at the GaAs top surface increased significantly from 0.14 to 3.2μm-1 while the O and C dose at Si/GaAs interface increased from 7.3x1011 to 4.0x1012 atoms/cm2 and from 1.9x1014 to 1.7x1015 atoms/cm2, respectively. [2] By optimizing the process, the GaAs top surface can be virtually APB free with total thickness as thin as 150nm. The electrical and optical properties of GaAs film can be greatly improved when APB is eliminated. Hall Effect measurements revealed a mobility enhancement from 200 to 2000 cm2/V.s. The room temperature photoluminescence (PL) intensity increased almost 10 times. [3] Planar ultrathin InAs-channel MOSFETs were demonstrated on Si substrates with gate lengths (Lg) as small as 20 nm which showed high transconductance about 2000 μS/μm at VDS=0.5V and 142 mV/dec subthreshold swing (SS). The III-V buffer layers were grown on 300 mm Si substrates by MOCVD and the subsequent InAlAs bottom barriers and InAs channel were grown by MBE. [4] Selective growth on patterned wafers can benefit from defect trapping in high aspect ratio structures. We successfully grew high quality GaAs, InGaAs and InAlAs layers in both narrow and wide trenches ranging from tens of nanometers to hundreds of nanometers. [5-7] It’s shown that the APB density is lower in higher aspect ratio trenches. InxGa1-xAs (x=0.1-0.4) quantum wells with stack GaAs/AlAs/InGaAs/AlAs/GaAs in 100nm wide trenches were demonstrated and room temperature μPL spectra were observed. We also explored the concept of III-V FinFET devices which uses InGaAs as channel layer. Reference [1] Y. Bogumilowicz, et al., Applied Physics Letters 107, 212105 (2015). [2] C. Barrett, et al., Journal of Materials Science 51, 449-456 (2016). [3] R. Alcotte, et al., APL Materials 4, 046101 (2016). [4] C. Y. Huang, et. al., International Symposium VLSI Technology, Systems and Application (2015). [5] W. Guo, et al., Applied Physics Letters 105, 062101 (2014). [6] R. Cipro, et al., Applied Physics Letters 104, 262103 (2014). [7] B. Wood, et al., International Symposium VLSI Technology, Systems and Application (2015).

Review on formation mechanism of chemical reaction layer during chemical mechanical polishing of monocrystalline SiC and sapphire substrates

Chemical mechanical polishing/planarization (CMP) of wafers is routinely used as the last mechanical process to produce super-smooth or critically planarized surfaces by removing machining-induced surface/subsurface damages and at the same time reduce the surface roughness to the level nanometers or even sub-nanometers without sacrificing the overall flatness. Successful CMP of monocrystalline silicon carbide (SiC) and sapphire substrates—two major substrates besides silicon for fabrication of high-brightness light emission diode (LED) devices, and also two important optical materials for space applications—demands a deeper mechanistic understanding into the CMP material removal process of these two materials. One of crucial challenges is to reveal the mechanism of formation of the chemical reaction layer affected by chemical-mechanical interaction during CMP. This paper critically reviews the current status of relevant progresses, controversies and challenges. First, we reviewed the debate about the thermodynamic behavior of formation of the chemical reaction layer by carefully comparing the original experimental results and arguments by different groups, including numerous studies on the equilibrium of the reactions involved and the stable reaction products. Second, the inconsistencies on the reaction kinetic behavior of formation and removal of the reaction layer, i.e., the temperature dependent materials removal rates in terms of activation energy, were critically compared and re-analyzed by deriving the numerical values of activation energy from the existing literature. Third, the challenge in establishing the model CMP substrate systems was highlightened in order to stress the urgent requirement for a firm foundation without which the results of different labs were difficult to be critically compared. Last, problems of incomplete characterization of the structure and compositions of the reaction layer and substrates as well as the poor cross-lab repeatability of characterization results were discussed with examples. In the perspective part, we propose a few directions for possible breakthroughs in the area of the mechanisms of formation of the chemical reaction layer: (1) establishment of reliable model CMP substrate systems with controlled surface structure by taking into account a few key parameters including surface/ subsurface defect density, misorientation angle (off-cut angle) as well as crystallography planes exposed; (2) determination and control of the reaction rate to facilitate decoupling reaction and diffusion processes with the help of the frictional force microscopy technique. A multidisciplinary strategy for addressing the issues discussed above is thus strongly advocated through combining materials/surface science/chemistry related approaches—careful and detailed characterization using a variety of state-of-the-art analytical techniques, precise control of surface structure and defects for developing model CMP substrate systems, in-depth analyses of surface structure and compositions, chemical thermodynamic and kinetic studies on chemical reaction mechanisms, as well as microscopic frictional/wear tests and surface force measurements. This review will also have important implications for CMP processing of many more different types of materials other than sapphire and SiC, including but not limited to other promising LED substrates such as GaN and ZnO, optical materials for laser inertial confinement fusion applications such as hard-brittle fused silica and soft-brittle KDP crystals, as well as conventional and novel ceramics and crystals for strong lasers such as YAG and sesquioxides (Lu2O3, Y2O3).

Orientation alignment of epitaxial LiCoO2 thin films on vicinal SrTiO3 (100) substrates

LiCoO2 is epitaxially grown on SrTiO3 (100) substrates with (104) orientation. Because the LiCoO2 film is grown with its c-axis parallel to four equivalent 〈111〉 axes of the SrTiO3, the (104)-oriented film exhibits four-domain structure on the SrTiO3 (100) substrate. Introducing off-cut angle to the substrate surface breaks the equivalency between the four 〈111〉 axes of the SrTiO3 substrate to induce preferential growth of specific orientation with the c-axis in a descending direction of off-cut surface. Increasing off-cut angle and lowering deposition rate promote the preferential growth, because they facilitate step-flow growth mode, and finally align the c-axes in the domains completely into one 〈111〉 direction of the SrTiO3 substrate. The LiCoO2 film delivers a discharge capacity of 90 mAh g−1 at a low discharge rate of 0.01 C, and 25% of capacity is kept even at a high rate of discharge with 100 C.

Effect of substrate offcut angle on BGaN epitaxial growth

Researchers expect the material BGaN to be useful in neutron detectors and ultraviolet (UV) light-emitting devices. In this study, we investigate the effect of the substrate offcut angle and polarity upon BGaN growth. In particular, BGaN is grown on top of GaN upon Al2O3 substrates with various offcut angles. In the case of Ga-polar BGaN growth, the BN mole fraction increases as the offcut angle increases. Furthermore, as the offcut angle increases, the terrace width becomes reduced, which inhibits the formation of nuclei on the terrace and promotes the incorporation of B atoms at the step edges. Such incorporation is important at the step edge (which is the stable site) during BGaN growth because B atoms are easily desorbed from the surface and easily react in the gas phase. In the case of N-polar BGaN growth, the BN mole fraction exhibits different behavior in response to the offcut angle of the substrate. For this reason, the surface of N-polar BGaN is different from that of Ga-polar BGaN as it has facets of N-polar GaN and step bunching. These results indicate that the incorporation of B atoms at step edges significantly affects the BN mole fraction in BGaN growth.

Homogeneity improvement of N-polar InGaN/GaN multiple quantum wells by using c-plane sapphire substrate with off-cut-angle toward a-sapphire plane

To improve the homogeneity of the N-polar (−c-plane) InGaN/GaN multiple quantum wells (MQWs) grown by metalorganic vapor phase epitaxy (MOVPE), the growth of GaN and MQW on two c-plane sapphire substrates with an off-cut angle of 0.8° toward the a-plane (sub-A) and the m-plane (sub-M) was performed. The effects of the off-cut direction on the structural properties and surface morphologies of −c-plane GaN films were elucidated. It was found that the step bunching and meandering of −c-plane GaN were significantly suppressed on sub-A. The spatial homogeneity of the −c-plane InGaN/GaN MQWs along the off-cut direction was observed in the submicrometer scale using microbeam X-ray diffraction. By inhibiting the step bunching of the GaN template using sub-A, the thickness homogeneity of the MQWs on sub-A has been significantly improved in comparison with that on sub-M.

Anti-phase boundaries–Free GaAs epilayers on “quasi-nominal” Ge-buffered silicon substrates

We have obtained Anti-Phase Boundary (APB) free GaAs epilayers on “quasi-nominal” (001) silicon substrates, while using a thick germanium strain relaxed buffer between the GaAs layer and the silicon substrate in order to accommodate the 4% lattice mismatch between the two. As silicon (001) substrates always have a small random offcut angle from their nominal surface plane, we call them “quasi-nominal.” We have focused on the influence that this small (≤0.5°) offcut angle has on the GaAs epilayer properties, showing that it greatly influences the density of APBs. On 0.5° offcut substrates, we obtained smooth, slightly tensile strained (R = 106%) GaAs epilayers that were single domain (e.g., without any APB), showing that it is not necessary to use large offcut substrates, typically 4° to 6°, for GaAs epitaxy on silicon. These make the GaAs layers more compatible with the existing silicon manufacturing technology that uses “quasi-nominal” substrates.

Kinetic surface roughening and wafer bow control in heteroepitaxial growth of 3C-SiC on Si(111) substrates.

A thin, chemically inert 3C-SiC layer between GaN and Si helps not only to avoid the “melt-back” effect, but also to inhibit the crack generation in the grown GaN layers. The quality of GaN layer is heavily dependent on the unique properties of the available 3C-SiC/Si templates. In this paper, the parameters influencing the roughness, crystalline quality, and wafer bow are investigated and engineered to obtain high quality, low roughness 3C-SiC/Si templates suitable for subsequent GaN growth and device processing. Kinetic surface roughening and SiC growth mechanisms, which depend on both deposition temperature and off-cut angle, are reported for heteroepitaxial growth of 3C-SiC on Si substrates. The narrower terrace width on 4° off-axis Si enhances the step-flow growth at 1200 °C, with the roughness of 3C-SiC remaining constant with increasing thickness, corresponding to a scaling exponent of zero. Crack-free 3C-SiC grown on 150-mm Si substrate with a wafer bow of less than 20 μm was achieved. Both concave and convex wafer bow can be obtained by in situ tuning of the deposited SiC layer thicknesses. The 3C-SiC grown on off-axis Si, compared to that grown on on-axis Si, has lower surface roughness, better crystallinity, and smaller bow magnitude.

Growth and kinetic Monte Carlo simulation of InAs quantum wires on vicinal substrates

Self-assembled quantum structures have been successfully grown for some time now but control over their uniformity has proven difficult due to the stochastic nature of surface diffusion. We have investigated the effect of vicinal InP(001) substrates on the uniformity of InAs quantum wires grown on InGaAlAs lattice-matched to InP using molecular beam epitaxy. Dense quantum wires were grown on both nominally flat and vicinal substrates off-cut by 0.9° toward the [110] direction for comparison. The off-cut angle was chosen to provide terraces which match the orientation and spacing of wires grown on nominally flat substrates. A modest but statistically significant improvement in the size distribution of the wires was observed on vicinal substrates through the analysis of ultrahigh resolution scanning electron micrographs. The interface between the wires and the off-cut substrate was studied using cross-sectional high resolution scanning transmission electron microscopy. In addition, a kinetic Monte Carlo model of epitaxial growth including full strain calculations was developed to further investigate the nucleation process. Using an anisotropic bond model to account for the surface energy of different crystallographic facets, our simulations produced wires similar to those observed experimentally while demonstrating the importance of anisotropic bonding compared to anisotropic diffusion. Growth on vicinal substrates is also simulated here and indicates that off-cut substrates should indeed improve the size distribution of quantum wires under proper growth conditions.

Effects of Miscut Substrates on Electrical Conductivity Across InP and GaAs Wafer-Bonded Structures

Wafer bonding of GaAs and InP using an (NH4)2S treatment are investigated for the effect of the wafer offcut angle on the electrical conductivity of wafer-bonded III-V interfaces. HRTEM and STEM are used to confirm the misorientation of the bonded samples and to compare the interface morphology across the range of relative misorientations. A line ratio at the interface shows that the well-bonded crystalline regions to amorphous oxide inclusions is consistent across all bonded samples, indicating that the degree of misorientation does not affect the level of interface recrystallization at high temperatures. Fitting the zero-bias conductance over a range of temperatures reveals an increase in barrier heights for samples with greater than 4° misoriented bonded pairs. This demonstrates that the out-of-plane relative surface misorientation is a critical parameter to be monitored and thus any in-plane twist as well in order to achieve superior electrical conductivity in direct-bonded multijunction solar applications.

Effects of Miscut Substrates on Electrical Conductivity Across InP and GaAs Wafer-Bonded Structures

Direct wafer bonding of III-V materials is of great interest for the fabrication of next generation high efficiency solar cells. Traditional wafer bonding methods of III-V materials lead to highly unstable oxide interfaces and poor electrical properties. To resolve these issues, elevated annealing temperatures (>600 °C), long times, and large compressive forces are employed to break up this interfacial oxide layer, so that there is better contact between the III-V bonding interfaces. These harsh processing conditions ultimately limit the achievable efficiencies, due to dopant diffusion and residual thermal strains in processed devices. Sulfur surface treatment prior to bonding was found to reduce the inclusion unfavorable oxides at the interface, reducing the post-bonding thermal and compressive force requirements, and promoting the ability to bond large (100 mm diameter) wafers.. Various combinations of sulfur treated n-GaAs and n-InP directed bonded structures were measured to investigate the effects of offcut angles on the electrical conductivity. The impact of the relative offcut angle on the electrical properties is an new unexplored area which is of important issuece, as misorientated substrates are typically used for the growth of III-V epitaxial layers in the solar industry to avoid anti-phase boundaries. It is observed in both the GaAs and InP bonded structures, that out-of-plane relative surface orientations between the (001) planes that are greater than 4° exhibit non-ohmic behavior. A theoretical model that describes the electron tunneling across a grain boundary between semiconductor bicrystals is used to represent the bonded interface and estimate the barrier conduction height. Fitting the zero-bias conductance over a range of temperatures reveals an increase in barrier heights for samples with greater than 4° misoriented bonded pairs, correspondingly the interface resistance at room temperature increases. These results demonstrate that the out-of-plane relative surface misorientation is the critical parameter to be monitored in order to achieve superior electrical conductivity in direct-bonded multijunction solar applications. In addition, differences between GaAs-GaAs bonded structures and InP-InP bonded structures indicate that the barrier for GaAs-GaAs is significantly greater than for InP-InP. The impact of the miscut itself, however, is similar in both cases, showing that both the chemical nature and the structural interface properties play roles in trans-interface electrical conduction.

Homo-Epitaxial Growth on Low-Angle Off Cut 4H-SiC Substrate

The growth of 4H-SiC epilayers on 1.28o off-cut substrates is reported in this study and comparison when using standard 4o and 8o off-cut substrates is added. Growth at high temperature is needed for the polytype stability, whereas low C/Si is requested to decrease both triangular defects density and roughness of the grown surface. An in-situ etching with Si rich ambient allows the growth of epilayers with specular surface. The formation of Si droplets can be observed on the grown surfaces when lowering the growth temperature and appears first for the high off-cut angle.

Experimental verification of the model by Klapper for 4H-SiC homoepitaxy on vicinal substrates

4H-SiC homoepitaxial layers free of basal plane dislocations (BPDs) are urgently needed to overcome the so-called bipolar degradation of high-voltage devices. BPDs being present in substrates are able to either propagate to the epilayer or convert to harmless threading edge dislocations (TEDs) in the epilayer. The model by Klapper predicts the conversion of BPDs to TEDs to be more efficient for growth on vicinal substrates with low off-cut angle. This paper aims to verify the model by Klapper by an extensive variation of epitaxial growth parameters and the substrates' off-cut. It is shown that the off-cut angle is the key parameter for growth of BPD-free epilayers. Furthermore, it is shown that the model also describes adequately the behavior of different types of TEDs, i.e., TED II and TED III dislocations, during epitaxial growth. Therefore, the model by Klapper is verified successfully for 4H-SiC homoepitaxial growth on vicinal substrates.

Step-controlled homoepitaxial growth of 4H–SiC on vicinal substrates

A comprehensive study on the step-controlled homoepitaxial growth on the (0001)Si-face of vicinal 4H–SiC substrates was performed in order to establish epitaxial growth on 2° towards 〈112¯0〉 off-cut substrates and 4° towards 〈11¯00〉 off-cut substrates. A standard epitaxial growth process was developed by optimizing the growth temperature T, Si/H ratio and C/Si ratio for growth on 4° towards 〈112¯0〉 off-cut substrates. Thereby, step-controlled epitaxial growth was achieved within a broad operating window. The surface roughness of such epilayers varies typically between rms=0.5nm and rms=2.5nm and step-controlled growth is conserved even at a growth rate of 27μm/h. Then, the standard growth process was applied to substrates with different off-cut angles α of 2°, 4° and 8° as well as with different off-cut directions 〈112¯0〉 and 〈11¯00〉. The step-controlled growth was achieved also within a wide range of Si/H ratio and C/Si ratio for growth on 8° and 4° off-cut substrates, but the process window narrows strongly for growth on 2° off-cut substrates. The epilayers' surface roughness increases with decreasing off-cut angle of the substrate. Epilayers grown on 4° towards 〈11¯00〉 off-cut substrates were significantly smoother than epilayers grown on 4° towards 〈112¯0〉 off-cut substrates. No influence of the substrates' off-cut angle and direction on the growth rate was found. The experimental results of this comprehensive study are discussed globally in consideration of other relevant publications.

Electrical Conductivity of Direct Wafer-Bonded GaAs/GaAs Structures for Wafer-Bonded Tandem Solar Cells

Wafer bonding of GaAs using an ammonium sulfide (NH4)2S treatment is investigated for various structures. The effect of the wafer offcut angle on the electrical conductivity of III-V solar cell devices using n-GaAs/n-GaAs wafer-bonded structures is studied. High resolution x-ray diffraction is used to confirm the misorientation of the bonded samples. Additionally, we compare the electrical properties of epitaxially grown p-n junctions on GaAs to n-GaAs/p-GaAs wafer-bonded structures. High resolution transmission electron microscopy (HRTEM) and scanning transmission electron microscopy (STEM) are used to compare the interface morphology across the range of relative misorientations after a 600 {degree sign}C RTP. The ratio of well-bonded crystalline regions to amorphous oxide inclusions is consistent across all bonded samples, indicating that the degree of misorientation does not affect the level of interface recrystallization at high temperatures.

Quantitative Comparison Between Dislocation Densities in Offcut 4H-SiC Wafers Measured Using Synchrotron X-ray Topography and Molten KOH Etching

Molten KOH etching and x-ray topography have been well established as two of the major characterization techniques used for observing as well as analyzing the various crystallographic defects in both substrates and homoepitaxial layers of silicon carbide. Regarding assessment of dislocation density in commercial wafers, though the two techniques show good consistency in threading dislocation density analysis, significant discrepancy is found in the case of basal plane dislocations (BPDs). In this paper we compare measurements of BPD densities in 4-inch 4H-SiC commercial wafers assessed using both etching and topography methods. The ratio of the BPD density calculated from topographic images to that from etch pits is estimated to be larger than 1/sinθ, where θ is the offcut angle of the wafer. Based on the orientations of the defects in the wafers, a theoretical model is put forward to explain this disparity and two main sources of errors in assessing the BPD density using chemical etching are discussed.

Surface Observation of 4H-SiC (0001) Planarized by Catalyst-Referred Etching

We have developed a novel planarization method called catalyst-referred etching (CARE), which can planarize SiC substrates without the use of an abrasive. In this method, platinum is used as an oxidation catalyst. The surface of CARE-processed 4H-SiC (0001) substrates are atomically flat all over the wafer. It is found that the surface of CARE-processed substrates is composed of alternating wide and narrow terraces with single bilayer-height steps, regardless of the off-cut angle. This unique structure is induced by the differences in the chemical stabilities of the terraces.