Off-axis 4H-SiC Substrates Research Articles

Layered Epitaxial Growth of 3C/4H Silicon Carbide Confined by Surface Micro-Nano Steps

In this study, we used a horizontal hot-wall CVD epitaxy apparatus to grow epitaxial layers on 4° off-axis 4H-SiC substrates. Epitaxial films were grown by adjusting the flow rate of the source gas at different levels. With an increase in the source gas flow rate, a notable transition in the crystalline structure of the epitaxial layer was observed, gradually shifting from 4H-SiC to 3C-SiC. Furthermore, the quality of the epitaxial layer correspondingly exhibited degradation. Specifically, for epitaxial films grown under moderate gas flow rates, the central region demonstrated a crystalline structure of 4H-SiC, while the outer ring region exhibited a crystalline structure of 3C-SiC. Using a scanning electron microscope (SEM) to observe the transition zone of the two regions, a region of 3C/4H overlapping growth below it was found. Bright areas corresponded to 3C, while dark areas corresponded to 4H, as confirmed by Raman spectroscopy and other SEM images. The growth interfaces of the two crystal types were clearly discernible and relatively compact. Furthermore, the growth angles of the two crystal types and their correlation with the cutting direction strongly suggest that this overlap is related to the formation of micro-nano steps on the substrate surface.

Step flow growth of β-Ga2O3 films on off-axis 4H-SiC substrates by LPCVD

In this work, β-Ga2O3 films were prepared on 4H-SiC (0001) substrates with 4° off-axis by low-pressure chemical vapor deposition (LPCVD). The crystalline structures, chemical compositions, optical properties, and surface/interface of the as-prepared films and heterostructures were all comprehensively investigated. X-ray diffraction and room temperature Raman spectrometry demonstrated β-Ga2O3 films are pure phase with highly preferential growth orientation along the (-201) plane. The Ga/O ratio estimated by X-ray photoelectron spectroscopy was 0.7, indicating the existence of Ga-O bonding. In addition, β-Ga2O3 films showed high transmittance at wavelengths over 300 nm, corresponding to an optical bandgap of about 4.88 eV. Remarkably, the growth of β-Ga2O3 films on 4H-SiC substrates with 4° off-axis followed the step-flow growth mode, reported for the first time. The relevant growth mechanism was discussed. These results demonstrated the feasible formation of heteroepitaxial growth of β-Ga2O3 films with high crystal quality and superior electrical properties on 4H-SiC substrates with off-axis angle by LPCVD, promising for applications in Ga2O3 based high power and optoelectronic devices.

High quality epitaxial graphene on 4H-SiC by face-to-face growth in ultra-high vacuum

Epitaxial graphene on SiC is the most promising substrate for the next generation 2D electronics, due to the possibility to fabricate 2D heterostructures directly on it, opening the door to the use of all technological processes developed for silicon electronics. To obtain a suitable material for large scale applications, it is essential to achieve perfect control of size, quality, growth rate and thickness. Here we show that this control on epitaxial graphene can be achieved by exploiting the face-to-face annealing of SiC in ultra-high vacuum. With this method, Si atoms trapped in the narrow space between two SiC wafers at high temperatures contribute to the reduction of the Si sublimation rate, allowing to achieve smooth and virtually defect free single graphene layers. We analyse the products obtained on both on-axis and off-axis 4H-SiC substrates in a wide range of temperatures (1300 °C–1500 °C), determining the growth law with the help of x-ray photoelectron spectroscopy (XPS). Our epitaxial graphene on SiC has terrace widths up to 10 μm (on-axis) and 500 nm (off-axis) as demonstrated by atomic force microscopy and scanning tunnelling microscopy, while XPS and Raman spectroscopy confirm high purity and crystalline quality.

Strain Release in GaN Epitaxy on 4° Off-Axis 4H-SiC.

A hybrid field-effect transistor (HyFET), superior for power electronic applications, can be created by harnessing the merits of two representative wide-bandgap semiconductors, gallium nitride (GaN) and silicon carbide (SiC). Yet, the incompactness in the epitaxy techniques hinders the development of the HyFET-GaN is usually grown on on-axis foreign substrates including SiC, whereas SiC homoepitaxy prefers off-axis substrates. This work presents a GaN-based heterostructure epitaxially grown on a conventional 4° off-axis 4H-SiC substrate, which manifests its high quality and suitability for constructing GaN-based high-electron-mobility transistors, thereby suggesting a practical approach to realizing HyFETs. In the meanwhile, a distinct two-step biaxial strain-relaxation process is proposed and studied with comprehensive characterizations.

Effects of annealing on the interfacial properties and energy-band alignment of AlN dielectric on 4H–SiC

Interfacial properties and energy-band alignment of annealed AlN dielectric films on Si-face 4° off-axis 4H–SiC substrates were characterized and demonstrated by x-ray photoelectron spectroscopy (XPS) and current-electric field (I–E) measurements. The XPS results reveal that the Al–O bonds and the silicon suboxides can convert into more stable Al–N bonds and Al–O–Si bonds at the AlN/4H–SiC interface under 1000 °C annealing. The variations in both oxygen-rich composition and the crystallinity in AlN make annealing-dependent conduction band offsets of as-deposited and annealed AlN/4H–SiC to be 1.36 eV and 1.20 eV, respectively. Meanwhile, I–E measurements separately yield the occurrence of the Fowler–Nordheim (FN) tunneling and space-charge-limited conduction in as-deposited and annealed metal-insulator-semiconductor capacitors, corresponding to lower barrier heights of 0.92 eV and 0.54 eV, respectively. The reason for the energy-band shift between I–E derivations and the XPS results was analyzed and demonstrated together. These results can provide considerable insight into the energy-band alignment of AlN as gate dielectric or passivation layers on 4H–SiC based devices.

A patterning-free approach for growth of free-standing graphene nanoribbons using step-bunched facets of off-oriented 4H-SiC(0 0 0 1) epilayers

The tunable electronic structure of graphene nanoribbons (GNRs) has attracted much attention due to the great potential in nanoscale electronic applications. Most methods to produce GNRs rely on the lithographic process, which suffers from the process-induced disorder in the graphene and scalability issues. Here, we demonstrate a novel approach to directly grow free-standing GNRs on step-bunched facets of off-oriented 4H-SiC epilayers without any patterning or lithography. First, the 4H-SiC epilayers with well-defined bunched steps were intentionally grown on 4 degree off-axis 4H-SiC substrates by the sublimation epitaxy technique. As a result, periodic step facets in-between SiC terraces were obtained. Then, graphene layers were grown on such step-structured 4H-SiC epilayers by thermal decomposition of SiC. Scanning tunneling microscopy (STM) studies reveal that the inclined step facets are about 13–15 nm high and 30–35 nm wide, which gives an incline angle of 23–25 degrees. LEEM and LEED results showed that the terraces are mainly covered by monolayer graphene and the buffer layer underneath it. STM images and the analysis of their Fourier transform patterns suggest that on the facets, in-between terraces, graphene is strongly buckled and appears to be largely decoupled from the surface.

Growth of high-quality 4H-SiC epitaxial layers on 4° off-axis C-face 4H-SiC substrates

• 4H-SiC epilayers are prepared on C-face substrates. • Surface morphologies show a strong dependence on the growth conditions. • A specular surface morphology was obtained. 4H-Silicon carbide (SiC) epitaxial layers on the C-face SiC substrates are potentially useful for fabricating high-performance power SiC MOSFET device applications. In this research, 4H-SiC epilayers are prepared on 4° off-angle C-face 4H-SiC substrates through a low pressure chemical vapor deposition (CVD). Surface morphologies of the epilayers show a strong dependence on C/Si ratio, growth temperature and etching time. A specular surface morphology was obtained at the temperature of about 1550 °C, with the etching time of 15 min and C/Si ratio of 1.2.

Electrical Characterisation of Thick 3C-SiC Layers Grown on Off-Axis 4H-SiC Substrates

300 μm thick 3C-SiC epilayer was grown on off-axis 4H-SiC(0001) substrate with a high growth rate of 1 mm/hour. Dry oxidation, wet oxidation and N2O anneal were applied to fabricate lateral MOS capacitors on these 3C-SiC layers. MOS interface obtained by N2O anneal has the lowest interface trap density of 3~4x1011 eV-1cm-2. Although all MOS capacitors still have positive net charges at the MOS interface, the wet oxidised sample has the lowest effective charge density of ~9.17x1011 cm-2.

Investigation of Nanocutting Characteristics of Off-Axis 4H-SiC Substrate by Molecular Dynamics

Silicon carbide (SiC), especially 4H-SiC, is an ideal semiconductor in power electronics due to its outstanding electrical and thermal properties. It has high hardness and brittleness, which makes it difficult to machine. To understand the nanomachining characteristics of off-axis 4H-SiC and provide suggestions on 4H-SiC substrate thinning, the nanocutting process of 4 ∘ off-axis 4H-SiC was simulated by molecular dynamics. The results showed that the stacking fault induced by cutting propagates in the basal plane, and propagates deep into the SiC workpiece when the angle between the cutting direction and the c-axis is smaller than 90 ∘ . Bond reconstruction is found near the slip plane. The cutting depth is also a key parameter in nanocutting. With smaller cutting depth, machining is more like scratching than cutting. With larger cutting depth, more atoms are involved in the cutting, cutting force and workpiece temperature are higher, and more defects exist.

The influence of temperature on the silicon droplet evolution in the homoepitaxial growth of 4H-SiC

The homoepitaxial growth of 4H-SiC epilayers were conducted by hot-wall vertical chemical vapor deposition (CVD). The dependence of silicon droplets on the growth temperature on 4° off-axis 4H-SiC substrates and its mechanism have been investigated, which were characterized by Nomarski optical microscope, scanning electronic microscope (SEM) and micro-Raman spectrometer. The results indicated that the silicon droplets were highly crystalline. It was also found that the silicon droplet generation could be suppressed by increasing the growth temperature, though the growth rate declined slightly.

Spatial variation of lattice plane bending of 4H-SiC substrates

Basal plane bending of on- and off-axis 4H-SiC substrates was measured by high-resolution X-ray diffractometry (HRXRD).

4H-SiC V-Groove Trench MOSFETs with Low Specific On-State Resistance and High Reliability

1. Introduction Silicon Carbide (SiC) MOSFETs have attracted attention as high performance power devices due to their unique material properties such as wide bandgap, high electric field strength, high saturation velocity, and high thermal conductivity. However, the obtained channel mobility (field effect mobility) of 5-30 cm2V-1s-1 is substantially lower than the bulk mobility (1000 cm2V-1s-1) because of the high SiO2/SiC interface state density (D it). Thus, the reduction of the interface states is the key issue in the development of SiC MOS devices. In order to improve the channel mobility, we proposed MOSFETs fabricated on the 4H-SiC(0-33-8) face which has the lower interface state density than the 4H-SiC(0001) face. In fact, a high channel mobility of 80 cm2V-1s-1was attained by using the superior MOS properties. 2. Device structure of the V-groove Trench MOSFETs We have proposed the V-groove trench MOSFETs (VMOSFETs) with the 4H-SiC{0-33-8} face as the trench sidewalls for the channel region. Furthermore, the buried p+regions below the trench bottom corner and the thick oxide layer at the trench bottom were employed. Both of these contribute to alleviate the electric field in the trench bottom oxide layer in order to realize high breakdown voltage over 1200V without gate oxide breakdown. The schematic cross-sectional view of the VMOSFET is shown in Fig.1 3. Device Fabrication Process The SiC epitaxial layer was grown on 4o off-axis n-type 4H-SiC(000-1) substrate by chemical vapor deposition (CVD). The n+, p+ and p-body regions were formed by P and Al ion implantation. The channel length is 0.6 mm along the trench sidewall. Thereafter, the V-groove structures with the 4H-SiC{0-33-8} sidewalls were fabricated through the thermochemical etching process in Cl2 ambient using a SiO2 mask. Gate oxide was thermally grown, followed by nitridation and post oxidation annealing (POA), resulting in an oxide thickness of about 50 nm. The source and drain contact metal were fabricated and alloyed at the temperature of 1000oC. The Al electrode was deposited on the alloyed contact metal. 4. Results and Discussion Figure 2 shows the static device characteristics. Figure 2 (a) shows the on-state forward I D-V DS characteristics of the VMOSFETs. The measured specific on-resistance in accordance with the active area size is 2.0 mΩ cm2 (V GS = 20 V, V DS = 1 V) at room temperature. As shown in fig. 2 (b), the breakdown voltage of above 1200 V is obtained. Figure 3 shows the on-state forward I D-V DScharacteristics of the VMOSFETs of 6.0-mm-square chip. A large current of 150 A is obtained with a single chip.Figure 4 shows the temperature dependence of the specific on-resistance of the V MOSFET and a planar DMOSFET on 4o off 4H-SiC(0001). The specific on-resistance of the DMOSFET decreases from -50oC to 0oC as expected due to the thermal emission of trapped electrons near oxide interfaces. In contrast, the specific on-resistance of the VMOSFET monotonically increases from -50oC to 175oC. This result shows that a drift resistance in the epitaxial layer of the VMOSFETs is more dominant than a channel resistance because of the low interface state density (D it) of SiO2/4H- SiC(0-33-8).We evaluated the stability of the threshold voltage of the VMOSFETs. Figure 5 shows the High Temperature Gate Bias (HTGB) test results of the VMOSFETs under a gate bias of +20V or -10V at 175oC. The threshold voltage of the VMOSFETs was 3 V (V DS = 10 V, I D = 5 mA cm-2). After the 1000 hour test, the threshold voltage shifts were only less than ±0.2 V of both positive and negative gate bias tests. These results show the excellent threshold voltage stability of the VMOSFETs for long term operation. This is considered due to the low interface trap density of SiO2/4H-SiC(0-33-8). 5. Summary The originally structured 4H-SiC V-groove trench MOSFET with the {0-33-8} face for the trench sidewalls has been proposed. The inclined trench structure can be fabricated by the thermochemical chlorine etching, resulting in the smooth low damage surface. Consequently, the low specific on-state resistance of the VMOSFET is attained. Thus a large current of 150A was obtained with a single 6-mm-square chip. Also High Temperature Gate Bias (HTGB) test was performed under a gate bias of +20V or -10V at 175oC. After the 1000 hour test, the threshold voltage kept stable with only less than ±0.2 V voltage shifts. Due to these advantages, the VMOSFETs are suitable for use in automotive electronic devices and the regenerative energy generation system applications. Figure 1

Chloride-based fast homoepitaxial growth of 4H-SiC films in a vertical hot-wall CVD**Project supported by the National High Technology R&D Program of China (No. 2014AA041402), the National Natural Science Foundation of China (Nos. 61474113, 61274007, 61574140), the Beijing Natural Science Foundation of China (Nos. 4132076, 4132074), the Program of State Grid Smart Grid Research Institute (No. SGRI-WD-71-14-004), and the Youth Innovation

Chloride-based fast homoepitaxial growth of 4H-SiC epilayers was performed on 4° off-axis 4H-SiC substrates in a home-made vertical hot-wall chemical vapor deposition (CVD) system using H2−SiH4−C2H4−HCl. The effect of the SiH4/H2 ratio and reactor pressure on the growth rate of 4H-SiC epilayers has been studied successively. The growth rate increase in proportion to the SiH4/H2 ratio and the influence mechanism of chlorine has been investigated. With the reactor pressure increasing from 40 to 100 Torr, the growth rate increased to 52 μm/hand then decreased to 47 μm/h, which is due to the joint effect of H2 and HCl etching as well as the formation of Si clusters at higher reactor pressure. The surface root mean square (RMS) roughness keeps around 1 nm with the growth rate increasing to 49 μm/h. The scanning electron microscope (SEM), Raman spectroscopy and X-ray diffraction (XRD) demonstrate that 96.7 μm thick 4H-SiC layers of good uniformity in thickness and doping with high crystal quality can be achieved. These results prove that chloride-based fast epitaxy is an advanced growth technique for 4H-SiC homoepitaxy.

Self-organized metal-semiconductor epitaxial graphene layer on off-axis 4H-SiC(0001)

The remarkable properties of graphene have shown promise for new perspectives in future electronics, notably for nanometer scale devices. Here we grow graphene epitaxially on an off-axis 4H-SiC(0001) substrate and demonstrate the formation of periodic arrangement of monolayer graphene on planar (0001) terraces and Bernal bilayer graphene on (112 — 0) nanofacets of SiC. We investigate these lateral superlattices using Raman spectroscopy, atomic force microscopy/ electrostatic force microscopy (AFM/EFM) and X-ray and angle resolved photoemission spectroscopy (XPS/ARPES). The correlation of EFM and ARPES reveals the appearance of permanent electronic band gaps in AB-stacked bilayer graphene on (112 — 0) SiC nanofacets of 150 meV. This feature is confirmed by density functional theory (DFT) calculations. The charge transfer between the substrate and graphene bilayer results in an asymmetric charge distribution between the top and the bottom graphene layers opening an energy gap. This surface organization can be thus defined as self-organized metal–semiconductor graphene.

Ge Assisted SiC Epitaxial Growth by CVD on SiC Substrate

This paper presents the results obtained after chemical vapor deposition of SiC with the addition of GeH4 gas to the classical SiH4+C3H8 precursor system. Epitaxial growth was performed either on 8°off-axis or on-axis 4H-SiC substrate in the temperature range 1500-1600°C. In the off-axis case, the layer quality (surface morphology and defect density) does not change though accompanied with Ge droplets accumulation at the surface. The Ge incorporation level was found to increase with temperature in the 1017 1018 cm-3 ranges. It was observed that adding GeH4 leads to the increase of the n type doping level by a factor from 2 to 5 depending on the C/Si ratio. In the on-axis case, GeH4 was only added to the gas phase before starting the SiC growth. It was found that there is a conditions window (temperature and GeH4 flux) for which 3C-SiC twin free layers can be grown. Adding this foreign element before SiC growth clearly modifies SiC nucleation on on-axis substrate.

Ge Mediated Surface Preparation for Twin Free 3C-SiC Nucleation and Growth on Low Off-Axis 4H-SiC Substrate

In this work, we report on the effect of adding GeH4 during 3C-SiC heteroepitaxial growth on low off-axis 4H-SiC substrate using chemical vapor deposition technique. When added together with SiH4 and C3H8, GeH4 does not significantly modify the 3C layer quality which contains a high density of twin boundaries. But when it is introduced before the growth, i.e. during a surface pretreatment step at 1500°C, a remarkable change in the layer morphology is seen. Furthermore for optimal GeH4 flux, twin boundaries are completely eliminated. Investigation of the results obtained when varying growth parameters (temperature, C/Si ratio, gas composition during the surface preparation) allowed proposing a mechanism leading to twin boundary elimination. It involves a transient homoepitaxial growth step followed by 3C nucleation when large terraces are formed by step faceting. Preliminary electrical characterizations of the twin free 3C-SiC layers, using conductive atomic force microscopy (c-AFM), are given.

Fast Homoepitaxial Growth of 4H-SiC Films on 4° off-Axis Substrates in a SiH4-C2H4-H2 System

Homoepitaxial growth of 4H-SiC epilayers is conducted in a SiH4-C2H4-H2 system by low pressure hot-wall vertical chemical vapor deposition (CVD). Thick epilayers of 45 μm are achieved at a high growth rate up to 26 μm/h under an optimized growth condition, and are characterized by using a Normaski optical microscope, a scanning electronic microscope (SEM), an atomic force microscope (AFM) and an x-ray diffractometer (XRD), indicating good crystalline quality with mirror-like smooth surfaces and an rms roughness of 0.9 nm in a 5 μm × 5μm area. The dependence of the 4H-SiC growth rate on growth conditions on 4° off-axis 4H-SiC substrates and its mechanism are investigated. It is found that the H2 flow rate could influence the surface roughness, while good surface morphologies without Si droplets and epitaxial defects such as triangular defects could be obtained by increasing temperature.

Formation of Epitaxial Defects by Threading Screw Dislocations with a Morphological Feature at the Surface of 4º Off-Axis 4H-SiC Substrates

In this paper, we present the formation of extended epitaxial defects, such as carrot defects, from threading screw dislocations (TSDs) with a morphological feature at the surface of the substrates. It was confirmed using highly sensitive surface observation, atomic force microscopy (AFM) and KOH etching that the surface roughness around a TSD was observed as the morphological feature and TSDs with such a morphological feature formed extended epitaxial defects with high frequency of appearance compared to usual TSDs without any features. The density of TSDs with such morphological feature depended on the polishing methods. Furthermore, we observed that the formation and shapes of extended defects from TSDs with such morphological feature were affected by step-bunching at the surface of the epilayers.

Surface Preparation of 4° Off-Axis 4H-SiC Substrate for Epitaxial Growth

Results of surface preparation on Si-face 4° off-cut 4H-SiC substrates are presented in this paper. The influences of two types of etchants, i.e. hydrogen chloride (HCl) and only hydrogen (H2), were investigated by Nomarski microscopy and AFM. The experiments were performed in a hot wall CVD reactor using a TaC coated susceptor. Four etching temperatures, including 1580 °C, 1600 °C, 1620 °C and 1640 °C, were studied. In-situ etching with only H2 as ambient atmosphere is found to be the optimal way for the SiC surface preparation. Using HCl at temperature higher than 1620 °C could degrade the substrates surface quality.

Effect of surface morphology on the electron mobility of epitaxial graphene grown on 0° and 8° Si-terminated 4H-SiC substrates

Graphene with different surface morphologies were fabricated on 8°-off-axis and on-axis 4H-SiC(0001) substrates by high-temperature thermal decompositions. Graphene grown on Si-terminated 8°-off-axis 4H-SiC(0001) shows lower Hall mobility than the counterpart of on-axis SiC substrates. The terrace width is not responsible for the different electron mobility of graphene grown on different substrates, as the terrace width is much larger than the mean free path of the electrons. The electron mobility of graphene remains unchanged with an increasing terrace width on Si-terminated on-axis SiC. Interface scattering and short-range scattering are the main factors affecting the mobility of epitaxial graphene. After the optimization of the growth process, the Hall mobility of the graphene reaches 1770 cm2/V·s at a carrier density of 9.8. × 1012 cm−2. Wafer-size graphene was successfully achieved with an excellent double-layer thickness uniformity of 89.7% on a 3-inch SiC substrate.