Electrical Characterisation of Thick 3C-SiC Layers Grown on Off-Axis 4H-SiC Substrates

Abstract

300 μm thick 3C-SiC epilayer was grown on off-axis 4H-SiC(0001) substrate with a high growth rate of 1 mm/hour. Dry oxidation, wet oxidation and N2O anneal were applied to fabricate lateral MOS capacitors on these 3C-SiC layers. MOS interface obtained by N2O anneal has the lowest interface trap density of 3~4x1011 eV-1cm-2. Although all MOS capacitors still have positive net charges at the MOS interface, the wet oxidised sample has the lowest effective charge density of ~9.17x1011 cm-2.