Occupied Silicon Area Research Articles

An Ultra-Low Power Fixed-Window Level Crossing ADC for ECG Recording.

In this paper, a novel fixed-window level-crossing analog-to-digital converter (LCADC) is proposed for the ECG monitoring application. The proposed circuit is implemented using fewer comparators and reference levels compared to the conventional structure, which results in a decrease in complexity and occupied silicon area. Also, the power consumption is reduced considerably by decreasing the activity of the comparator. Simulation results show a 5-fold reduction in activity by applying the standard ECG signals to the proposed structure. The proposed circuit is implemented in 0.18 µm CMOS technology using a 0.9 V supply voltage. Measurement results show a 5.9 nW power consumption and a 7.4-bit resolution. The circuit occupies a 0.05846 mm2 silicon area. A typical level-crossing-based R-peak-detection algorithm is applied to the output samples of the LCADC, which shows the effectiveness of using this type of sampling.

Thermal–Mechanical and Signal Reliability of a New Differentiated TSV

The thermal–mechanical and signal reliability of through-silicon via (TSV) occupies an important position in three-dimensional integrated circuits (3D-ICs). However, few studies combined the thermal–mechanical and signal reliability are found. In the work, a new differentiated structure of TSV is proposed to decrease the peak thermal stress without affecting signal integrity. The effect of TSV diameter on the peak thermal stress and its location is deeply investigated to decrease the stress. Compared with regular TSV, the differentiated TSV can reduce 22% peak thermal stress and 68% occupied silicon area. More differentiated TSVs can be placed in the same Si substrate by considering the influence of thermal stress between TSVs. Meanwhile, the differentiated TSV can better shield crosstalk noise with ensuring signal integrity.

Crosstalk Noise of Octagonal TSV Array Arrangement Based on Different Input Signal

This paper proposes an octagonal layout for enhancing the ability of resisting electromagnetic interference in Through Silicon Via (TSV) array. The influential factors of crosstalk noise between TSVs are investigated, including the TSV pitch, signal and ground TSVs location, and signal types (single-end and differential signal) by using a coplanar wave guide (CPW) testing structure. These results, based on traditional TSV arrays, show that a staggered TSV layout with differential signals had lower crosstalk noise. On this basis, the octagonal layout of TSV array is proposed and we show that it has obvious superiority in reducing occupied silicon area and crosstalk noise. Compared with traditional TSV arrays, the crosstalk noise is almost reduced by 44%. In order to further reduce the silicon area occupied by TSV without worsening crosstalk noise, the new division TSV structure is proposed in which a large TSV was substituted by four smaller TSVs. The area occupied by a single TSV and TSV array are both reduced by 60% without decreasing signal integrity when the regular TSV in the octagonal layout are replaced by a new TSV structure.

A Biomimetic Circuit for Electronic Skin With Application in Hand Prosthesis.

One major challenge in upper limb prostheses is providing sensory feedback to amputees. Reproducing the spiking patterns of human primary tactile afferents can be considered as the first step for this challenging problem. In this study, a novel biomimetic circuit for SA-I and RA-I afferents is proposed to functionally replicate the spiking response of the biological tactile afferents to indentation stimuli. The circuit has been designed, laid out, and simulated in TSMC 180nm CMOS technology with a 1.8V supply voltage. A pair of SA-I and RA-I afferent circuits consume [Formula: see text] of power. The occupied silicon area is [Formula: see text] for 32 afferents. To provide the inputs for circuit testing, a patch of skin with a grid of mechanoreceptors is simulated and tested by an edge stimulus presented at different orientations. Experimental data are collected using indentation of 3D-printed edges at different orientations on a tactile sensor mounted on a robotic arm. Inspired by innervation patterns observed in biology, the artificial afferents are connected to several neighboring mechanoreceptors with different weights to form complex receptive fields which cover the entire mechanoreceptor grid. Machine learning algorithms are applied offline to classify the edge orientations based on the pattern of neural responses. Our results show that the complex receptive fields arising from the innervation pattern led to smaller circuit area and lower power consumption, while facilitating data encoding from high-resolution sensors. The proposed biomimetic circuit and tactile encoding example demonstrate potential applications in modern tactile sensing modules for developing novel bio-robotic and prosthetic technologies.

An Area-Efficient DC Offset Cancellation Architecture for Zero-IF DVB-H Receivers

This letter presents a new dc offset cancellation structure for zero-IF receivers. A very small occupied area is the main advantage of this structure. The differential high-pass filter based on this structure, which has been implemented in the 0.18- $\mu \text{m}$ CMOS technology, achieves a lower cutoff frequency of 180 Hz. The occupied silicon area is less than 0.167 mm2. The gain variation of this filter is less than 0.3 dB at the frequency range of 700 Hz–3.8 MHz. Moreover, the IIP3 is better than 29 dBm. This filter draws 1.48 mA from the 1.8 V voltage supply, and it is able to tolerate ±45 mV input differential dc offset.

AN OPTIMIZED LOW POWER PIPELINE ANALOG-TO-DIGITAL CONVERTER FOR HIGH-SPEED WLAN APPLICATION

This paper presents the design and implementation of a 11-bit 160 MSPS analog-to-digital converter (ADC) for next generation super high-speed wireless local area network (WLAN) application. The ADC core consists of one front sample and hold stage and four cascades of 2.5 bit pipeline stages with opamp sharing between successive stages. To achieve low power dissipation at 1.2 V supply, a single stage symmetrical amplifier with double transimpedance gain-boosting amplifier is proposed. High speed on-chip reference buffer with replica source follower is also included for linearity performance. The ADC was fabricated in a standard 130-nm CMOS process and an occupied silicon area of 0.95 mm × 1.15 mm. Performance of 73 dB spurious-free-dynamic-range is measured at 160 MS/s with 1 Vpp input signal. The power dissipation of the analog core chip is only 50 mW from a 1.2 V supply.

A 53mW IQ pipelined ADC for WLAN front end

This paper presents an analog to digital converter (ADC) architecture suitable for wideband wireless receiver system. The in-phase (I) and quadrature (Q) ADCs work independently, but share on-chip reference buffer and non-overlapped clock generation block for balance between two channels. The single ADC core consists of one front sample and hold amplifier, four cascade of 2.5 bit pipeline stages with pseudo-class AB opamp shared between adjacent stages and one 2 bit backend flash stage. The prototype was fabricated in standard 130 nm CMOS process and occupied silicon area of 0.62 mm2. Performance of 66 dB spurious-free-dynamic-range is measured at 80 MS/s with 1 Vpp input signal. The power dissipation of the whole chip is only 53 mW from a 1.1 V supply.

Two-Phase Self-Assisted Zero-Voltage Switching DC–DC Converter

This paper proposes a two-phase self-assisted zero-voltage switching (ZVS) converter suitable for fully monolithic implementation. The proposed topology utilizes an auxiliary inductor connected between the two branches of a two-phase converter to achieve ZVS conditions. The proposed converter helps reduce the output voltage ripples of the standard ZVS topology. Furthermore, the auxiliary inductor could be magnetically coupled with the filtering inductor to reduce the occupied silicon area. The advantages of the proposed converter are validated through simulations on a 65-nm CMOS process.

Look-ahead sphere decoding: algorithm and VLSI architecture

Multiple-input-multiple-output (MIMO) systems are recognised as a key enabling technology in high-performance wireless communications; however, the implementation of high-throughput MIMO detectors still is a critical task. Among known MIMO detectors, sphere decoder algorithm (SDA) is capable of optimal performance with acceptable processing complexity. The study presents an improved SDA, which enables significant throughput increase at a very limited additional complexity and with no degradation in terms of bit error rate performance. The modified detection method, called LASDA (look-ahead SDA), is based on formal algorithm transformations, namely look-ahead, retiming and pipelining, and requires a modified tree search strategy. The VLSI design of LASDA detector supporting a 4 × 4 MIMO channel with 16 QAM modulation is detailed in the study for a 130 nm CMOS standard cell technology: synthesis results show that the proposed solution achieves an average throughput of 380 Mbps at a signal-to-noise ratio of 22 dB (Rayleigh fading channel), with an occupied silicon area of 0.18 mm 2 . Comparisons with a number of previous implementations are also provided.

Low-Power and Wide-Bandwidth Cyclic ADC With Capacitor and Opamp Reuse Techniques for CMOS Image Sensor Application

In this paper, a power-efficient programmable gain amplifier (PGA) and a cyclic analog-to-digital converter (ADC) are developed for a satellite CMOS image sensor system. The cyclic ADC employs capacitor and opamp reuse techniques to reduce power consumption and occupied silicon area. Moreover, a power-efficient and wide-bandwidth telescopic cascode gain boosting amplifier with capacitive level shifters is adopted to decrease its power consumption further. According to the system specification, a 10-bit, 14-MS/s cyclic ADC with the front-end PGA circuit is implemented in the TSMC 0.18- ?m triple-well 1P3M CMOS image sensor (CIS) process. The proposed cyclic ADC achieves a spurious free dynamic range (SFDR) of 65.1 dB and a signal-to-noise distortion ratio (SNDR) of 52.44 dB with 5-MHz input frequency at 14 MS/s. The power consumption of the cyclic ADC and PGA from a 3.3 V supply are 15.84 mW and 5.78 mW, respectively. The total core area is 0.381 mm2 .

CMOS multiband low-noise amplifier using inner diameter shared inductors

A new integrated inductor structure suitable for multiband application is proposed and used to implement a CMOS multiband low-noise amplifier. Its occupied silicon area can be decreased by more than 40% while its performance is almost the same as those of LNAs using the conventional inductor structure. It is fabricated in a 0.13 µm CMOS process and its measured results show gains of 16.8, 15.8 and 15.5 dB, with NFs of 1.4, 1.8 and 1.9 dB, and IIP3 of 4, 0 and −2 dBm for the 850, 1800/1900 and 2100 MHz bands, respectively.

A Low Power DVB-T/H Zero-IF Tuner IC Design in 0.25 $\mu{\hbox {m}}$ BiCMOS Technology for Mobile TV Reception

This paper describes fully integrated RF IC sub-system of a DVB-T/H receiver intended for Mobile TV reception. The architecture of the RF IC has been designed to be compliant with the category b2 & c of the MBRAIMoBile Radio Access Interface. specification developed for the introduction of TV into existing mobile phone. The coexistence with GSM transceivers has been taken into account to establish the complete link budget from UHF antenna down to the Digital Front-end. A broadband LNA has been designed for an overall IC noise figure of 3.9 dB. The IIP3 is -5 dBm while 25 dBm RF IIP2 has been measured. A 5th order low pass filter has been implemented for adjacent channel suppression. The total power consumption is 150 mW in continuous mode. Thanks to a new broadband synthesizer architecture using a single VCO, the occupied silicon area is 2.2 mm2 in a 0.25 mum BiCMOS technology

A CMOS Bandgap Reference Circuit for Sub-1-V Operation without Using Extra Low-Threshold-Voltage Device

A new sub-1-V CMOS bandgap voltage reference without using low-threshold-voltage device is presented in this paper. The new proposed sub-1-V bandgap reference with startup circuit has been successfully verified in a standard 0.25-μm CMOS process, where the occupied silicon area is only 177 μm x 106 μm. The experimental results have shown that, with the minimum supply voltage of 0.85 V, the output reference voltage is 238.2 mV at room temperature, and the temperature coefficient is 58.1 ppm/°C from-10°C to 120°C without laser trimming. Under the supply voltage of 0.85 V, the average power supply rejection ratio (PSRR) is -33.2 dB at 10kHz.

A cost-efficient high-speed 12-bit pipeline ADC in 0.18-/spl mu/m digital CMOS

A 12-bit pipeline ADC fabricated in a 0.18-/spl mu/m pure digital CMOS technology is presented. Its nominal conversion rate is 110 MS/s and the nominal supply voltage is 1.8 V. The effective number of bits is 10.4 when a 10-MHz input signal with 2V/sub P-P/ signal swing is applied. The occupied silicon area is 0.86 mm/sup 2/ and the power consumption equals 97 mW. A switched capacitor bias current generator scales the opamp bias currents automatically with the conversion rate, which gives scaleable power consumption and full performance of the ADC from 20 to 140 MS/s.