An Area-Efficient DC Offset Cancellation Architecture for Zero-IF DVB-H Receivers

Abstract

This letter presents a new dc offset cancellation structure for zero-IF receivers. A very small occupied area is the main advantage of this structure. The differential high-pass filter based on this structure, which has been implemented in the 0.18- $\mu \text{m}$ CMOS technology, achieves a lower cutoff frequency of 180 Hz. The occupied silicon area is less than 0.167 mm2. The gain variation of this filter is less than 0.3 dB at the frequency range of 700 Hz–3.8 MHz. Moreover, the IIP3 is better than 29 dBm. This filter draws 1.48 mA from the 1.8 V voltage supply, and it is able to tolerate ±45 mV input differential dc offset.