Number Of Through-silicon Vias Research Articles

A Cost-Driven Chip Partitioning Method for Heterogeneous 3D Integration

Three-dimensional integration circuit (3D IC) offers significant benefits in terms of performance and cost. Existing research in through-silicon via (TSV)-based 3D IC partitioning has focused on minimizing the number of TSVs to reduce costs. Partitioning methods based on heterogeneous integration have emerged as viable approaches for cost optimization. Leveraging mature processes to manufacture not timing-critical blocks can yield cost benefits. Nevertheless, none of the previous 3D partitioning work has focused on reducing the overall cost, including both design and manufacturing costs, for heterogeneous 3D integration. Moreover, throughput constraints have not been considered. This article presents a cost-aware integer linear programming-based formulation and a heuristic algorithm that partition the functional blocks in the design into different technological groups. Each group of functional blocks will be implemented using a particular process technology, and then integrated into a 3D IC. Our results show that 3D heterogeneous integration chip implementation can reduce overall cost while satisfying various timing constraints.

Fast power density aware three‐dimensional integrated circuit floorplanning for hard macroblocks using best operator combination genetic algorithm

AbstractIn this article, we propose a fast three‐dimensional integrated circuit (3D‐IC) floorplanning method for hard macroblocks that includes a thermal management scheme. It applies a genetic algorithm constituted by an optimal combination of crossover and mutation operations to identify the optimal solution for design variables, namely, total wire length, number of through‐silicon vias (TSVs), and maximum average layer power density. The proposed method additionally makes use of a unique TSV placement scheme that arranges TSVs next to their respective functional blocks. To enable efficient heat transmission to the ambient environment, layers with higher power densities are placed closer to the heat sink. The proposed 3D‐IC floorplanning approach provides the fewest TSVs, the lowest peak temperature, and promising values of wire length within the least amount of computation time. Compared to the recent fast thermal analysis for fixed‐outline 3D‐floorplanning, it generates 13.14% shorter wire length, 39.27% lower peak temperature, and 34.35% lesser number of TSVs on average with significant improvement in computation time, while analyzing GSRC thermal benchmark circuits.

Review of Bumpless Build Cube (BBCube) Using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI)

Bumpless Build Cube (BBCube) using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI) is discussed. Bumpless interconnects between wafers and between chips and wafers are a second-generation alternative to the use of micro-bumps for WOW and COW technologies. WOW and COW technologies for BBCube can be used for homogeneous and heterogeneous 3DI, respectively. Ultra-thinning of wafers down to 4 μm offers the advantage of a small form factor, not only in terms of the total volume of 3D ICs, but also the aspect ratio of Through-Silicon-Vias (TSVs). Bumpless interconnect technology can increase the number of TSVs per chip due to the finer TSV pitch and the lower impedance of bumpless TSV interconnects. In addition, high-density TSV interconnects with a short length provide the highest thermal dissipation from high-temperature devices such as CPUs and GPUs. This paper describes the process platform for BBCube WOW and COW technologies and BBCube DRAMs with high speed and low IO buffer power by enhancing parallelism and increasing yield by using a vertically replaceable memory block architecture, and also presents a comparison of thermal characteristics in 3D structures constructed with micro-bumps and BBCube.

Fast algorithms for test optimization of core based 3D SoC

The use of 3D-IC technology has become quite widespread in designing core-based systems-on-chip (SoCs). Concomitantly, testing of cores and inter-layer through-silicon-vias (TSVs) spanning through different layers of 3D chips has become an important problem in the manufacturing cycle. Testing 3D-SoCs is more challenging compared to their 2D counterparts because of the complexity of their design and power management issues. Also, the test procedure demands substantially more power than what is required in the normal functional mode, and hence, stringent thermal constraints during test need to be fulfilled to safeguard future performance and reliability of the chip. Since the overall 3D infrastructure depends on routing layer assignments, core allocation, and the geometry of TSV locations, these parameters should be given due consideration while designing the test-access-mechanism (TAM) that aims for minimizing overall test time satisfying power and TSV constraints. In this paper, we present a three-stage algorithm for reducing the test time in automated post-bond core-based 3D-SoCs, under a set of given constraints on test power, TAM-width, and the number of available TSVs. The proposed algorithm, when run on several ITC-02 SoC benchmarks, outperforms the algorithms presented in earlier work with respect to CPU-time, and additionally, reduces test time in many instances.

3D‐IC partitioning method based on genetic algorithm

In this study, a new tier partitioning algorithm for three-dimensional integrated circuits (3D ICs) using a genetic algorithm (GA) is presented. Design parameters for the proposed 3D IC partitioning method are average layer power density and number of through-silicon vias (TSVs) subject to fixed-outline constraint. The GA with newly introduced crossover and mutation operation, termed as even crossover and complement mutation, is employed for optimisation of design variables. Experimental results exhibit that the authors proposed method reduces the average number of TSVs by 45.75 and 44.68%, as compared to taboo search and simulated annealing-based 3D partitioning methods. It also reduces the average number of TSVs, maximum power density among the layers and average layer area by 28.34, 40.29, and 27.85%, respectively, as compared to thermal-aware 3D partitioning technique. The results of their proposed algorithm demonstrate the efficiency and effectiveness in tier partitioning for 3D ICs over existing methods.

TSV Optimized Test Wrapper Design for Fine Grain Partitioned 3D System on Chip

The 3D System-on-chip (SoC) technology supports the vertical interconnectivity required for the purpose of functional, supply and test access purposes through the use of Through Silicon Vias (TSVs). Little number of available TSVs for test purpose necessitates the optimization of test infrastructure. This paper proposes an algorithm to design the test wrapper for the 3D cores such that the number of the TSVs used per TAM chain are minimized. Test time optimization is done by balancing the lengths of the individual Wrapper chain inside the core. The proposed heuristic firstly distributes the different core elements on the given TAM chains and then uses a diagraph for their insertion ordering to get minimum possible TSV utilization. Simulation results are presented for the different cores of the ITC’02 SoC benchmark circuits. Results show that TSVs can be reduced to 20-30 percent with around 60-70 percent reduction in CPU time utilization for heavy SoCs in comparison to the other proposed techniques.

Co-Optimization of Test Wrapper Length and TSV for TSV Based 3D SOCs

In 3D IC, wrapper chains can span across vertical directions which causes the increase in number of TSVs(through-silicon-vias)(which is used to interconnect different cores in the vertical directions). Excessive use of TSVs in wrapper design causes routing congestion and additional overhead in manufacturing. Therefore, optimization of wrapper length and judicious use of TSVs are the focus of 3D wrapper architecture design. In this work, we first propose a heuristic procedure to determine the placement of wrapper elements in several layers of 3D SOC for a number of wrapper chains and interconnect them using available number of TSVs such that the length of the longest wrapper length (LWL) is minimized. Then we apply particle swarm optimization (PSO) based metaheuristic approach on the results obtained in first case to determine the placement of wrapper chains and interconnect them using minimum number of TSVs such that the length of LWL is minimized. We compare our results with earlier works and the experimental results show the efficacy of our algorithm.

Power and performance analysis of 3D network-on-chip architectures

Emerging 3D integrated circuits(ICs) employ 3D network-on-chip(NoC) to improve power, performance, and scalability. The NoC Simulator uses the microarchitecture parameters to estimate the power and performance of the NoC. We explore the design space for 3D Mesh and Butterfly Fat Tree(BFT) NoC architecture using floorplan drive wire length and link delay estimation. The delay and power models are extended using Through Silicon Via (TSV) power and delay models. Serialization is employed to reduce the TSV area cost. Buffer space is equalised for a fair comparison between topologies. The Performance, Flits per Joules(FpJ) and Energy Delay Product(EDP) of six 2D and 3D variants of Mesh and BFT topologies (two and four layers) are analyzed by injecting synthetic traffic patterns. The 3D-4L Mesh exhibit better performance, energy efficiency (up to 4.5 × ), and EDP (up to 98 %) compared to other variants. This is because the overall length of the horizontal link is short and the number of TSVs is large (3 × ).

MTL-based modeling and analysis of the effects of TSV noise coupling on the power delivery network in 3D ICs

With the application of heterogeneous integration and advanced packaging technologies, the use of through-silicon vias (TSVs) to deliver the power supply has become popular in the design of stacked chips in three-dimensional integrated circuits. High-density vertical interconnections offer higher speed and bandwidth, but the electromagnetic coupling effect among TSVs becomes more serious. Therefore, investigation of the noise coupling among TSVs and analysis of its impact on the power supply become important considerations. An analytical model based on the theory of multiconductor transmission lines (MTLs) is presented herein to discuss such TSV noise coupling. The method can accurately and quickly estimate the noise coupling coefficient among a large number of TSVs and offers good practicability for similar structures and even the TSVs of complex structures. Further, the influence of TSV noise coupling and simultaneous switching noise from switching circuits on the supplied power voltage is discussed. Finally, the parameters of an actual Intel chip are taken as an example to analyze the supplied power voltage that reaches complementary metal–oxide–semiconductor (CMOS) circuits through the three-dimensional (3D) power distribution network after considering the power supply noise. The presented model is validated by comparing the calculation results with those obtained from a full-wave simulator. The runtime and memory consumption requirements are lower than those of the full-wave simulator.

Virtualization-Based Efficient TSV Repair for 3-D Integrated Circuits

Three-dimensional (3-D) integration offers a promising solution to the technology scaling barriers. Reliability of the 3-D Integrated Circuits (ICs) is highly dependent on the integrity of the underlying interconnect. Through Silicon Via (TSV) based 3-D ICs would suffer from low yield due to the faults in TSVs. In addition, TSVs introduce stress and noise in the substrate. Adding redundant TSVs for repairing the faulty ones has commonly been proposed to improve the yield of TSV-based 3-D ICs. The existing TSV repair approaches employ a number of spare TSVs in a group of signal TSVs. We propose a TSV virtualization based repair architecture which utilizes a single redundant TSV to repair multiple faulty TSVs. The proposed architecture relies on transmitting multiple bits through a single TSV using multi-level voltage quantization. It makes efficient use of the TSV redundancies in repairing the faulty TSVs. With less number of spare TSVs, the proposed architecture can reduce the area overhead by more than 70%. Reduction in the TSV count allows greater interconnect density and helps to mitigate the TSV-induced noise and stresses. Alternatively, for a similar number of spare TSVs, the proposed method can enhance the fault tolerance capability of the conventional approaches thus leading to an enhanced chip yield. The eye diagram simulations using an electrical model of the TSV show a reduction of less than 5% in noise margin when using a 16-level voltage quantization at a data rate of 5 Gbps which is typical for 3-D integration applications.

Fast, Ring-Based Design of 3-D Stacked DRAM

As computer memory increases in size and processors continue to get faster, the memory subsystem becomes a bottleneck to system performance. To mitigate the relatively slow dynamic random access memory (DRAM) chip speeds, a new generation of 3-D stacked DRAM is being developed, with lower power consumption and higher bandwidth. This paper proposes the use of 3-D ring-based data fabrics for fast data transfer between the chips in the 3-D stacked DRAM. The ring-based data fabric uses a fast standing wave oscillator to clock its transactions. With a fast clocking scheme and multiple channels sharing the same bus, more channels are utilized while significantly reducing the number of through-silicon vias. Our memory architecture using a ring-based scheme (MARS) can effectively trade off power, throughput, and latency to improve the system performance for different application spaces. Experimental results show that our ring-based data fabric can reduce read latencies and power consumption. MARS variants can deliver better latency (up to $\sim 4\times $ ), power (up to $\sim 8\times $ ), and performance per watt (up to $\sim 8\times $ ) over high bandwidth memory. We also compare our approach with Wide I/O, which is designed for power-constrained systems. MARS variants provide better latency (up to $\sim 8\times $ ) with similar performance per watt.

A 3-D Rotation-Based Through-Silicon via Redundancy Architecture for Clustering Faults

Three-dimensional integrated circuits (3-D ICs), which feature many benefits, such as high bandwidth and a high degree of integration, have recently received considerable attention from the semiconductor industry. However, these chips feature through-silicon vias (TSVs), which vertically connect multiple dies, and these TSVs may fail, resulting in a decreased yield. Unfortunately, previously proposed methods to repair TSVs cannot handle certain failure patterns. For example, existing techniques cannot repair clustered TSV faults, which commonly occur in practice. Furthermore, the number of signal TSVs typically determines the number of redundant TSVs, which may result in wasteful and redundant TSVs. In this paper, a new TSV repair scheme is proposed that replaces defective TSVs with redundant TSVs by utilizing the architecture of a cube, which can replace any face with any of the other faces. Both signal TSVs and redundant TSVs are placed in the face of cube, so any faulted TSVs can be replaced with redundant TSVs. The experimental results indicate that the new method guarantees 100% coverage with any number of signal TSVs and redundant TSVs.

Low latency multicasting architecture implemented using new network topology

An important service in distributed systems, as multiprocessors, is the ability to transmit multicast messages. Cache coherence protocols and parallel algorithms are examples of applications requiring multicast messages. Several algorithms have been developed to implement multicasting namely the path based, and the tree based. These algorithms were able to ease the rapid saturation effect generated by such type of transmission. However, for some applications, these algorithms are not always efficient, and the multicast service might still generate the network saturation for low data loads. That's why recent studies have tried to apply these routing algorithms using a new network topology based on 3D integrated circuit technology (3DIC) . However, the 3DIC has not reached maturity because of the use of multiple number of TSV (through silicon vias).In this paper, we demonstrate the benefits of implementing adaptive multicast algorithm on a VRNOC architecture. Simulations and hardware synthesis results show that the proposed on-chip network architecture provides significant improvements in average network latency (15%) and resources (33% in number of links) than a fully 3D NOC.

Adaptive 3D-IC TSV Fault Tolerance Structure Generation

In 3-D integrated circuits (3D-ICs), through silicon via (TSV) is a critical technique in providing vertical connections. However, the yield is one of the key obstacles to adopt the TSV-based 3D-ICs technology in industry. Various fault-tolerance structures using spare TSVs to repair faulty functional TSVs have been proposed in literature for yield and reliability enhancement, but a valid structure cannot always be found due to the lack of effective generation methods for fault-tolerance structures. In this paper, we focus on the problem of adaptive fault-tolerance structure (AFTS) generation. Given the relations between functional TSVs and spare TSVs, we first calculate the maximum number of tolerant faults in each TSV group. Then we propose an integer linear programming-based model to construct the AFTS with minimal multiplexer delay overhead and hardware cost. We further develop a speed-up technique through an efficient min-cost-max-flow model. All the proposed methodologies are embedded in a top-down TSV planning framework to form functional TSV groups and generate AFTSs. Experimental results show that, compared with state-of-the-art, the number of spare TSVs used for fault tolerance can be effectively reduced.

Fast 3D Integrated Circuit Placement Methodology using Merging Technique

In the recent years the advancement in the field of microelectronics integrated circuit (IC) design technologies proved to be a boon for design and development of various advanced systems in-terms of its reduction in form factor, low power, high speed and with increased capacity to incorporate more designs. These systems provide phenomenal advantage for armoured fighting vehicle (AFV) design to develop miniaturised low power, high performance sub-systems. One such emerging high-end technology to be used to develop systems with high capabilities for AFVs is discussed in this paper. Three dimensional IC design is one of the emerging field used to develop high density heterogeneous systems in a reduced form factor. A novel grouping based partitioning and merge based placement (GPMP) methodology for 3D ICs to reduce through silicon vias (TSVs) count and placement time is proposed. Unlike state-of-the-art techniques, the proposed methodology does not suffer from initial overlap of cells during intra-layer placement which reduces the placement time. Connectivity based grouping and partitioning ensures less number of TSVs and merge based placement further reduces intra layer wire-length. The proposed GPMP methodology has been extensively against the IBMPLACE database and performance has been compared with the latest techniques resulting in 12 per cent improvement in wire-length, 13 per cent reduction in TSV and 1.1x improvement in placement time.

TSV Manufacturing Fault Modeling and Diagnosis Based on Multi-Tone Dither

The faults in through-silicon via (TSV) have a critical impact on the reliability and yield of a three-dimensional integrated circuit (3-D IC). With the significant increase in the number of TSVs used in 3-D IC, the testing of TSVs for manufacturing faults poses certain serious challenges especially weak fault testing, and therefore it is important to have effective Design-For-Test (DFT) techniques. In this paper, we present a method for TSV testing using multi-tone dither signal, based on electrical characteristic analysis. This method mainly observes the differences in the root mean square (RMS) value of the output signal voltage between faultless and faulty TSV circuits to detect manufacturing faults, and uses only passive components such as metal lines, without consuming additional power for the testing. With regard to the common manufacturing faults such as voids and pinholes, the electrical characteristics of faulty TSVs are modeled and analyzed, and analytic equations of the faults, which are based on characteristic parameters, are explored. The ground-signal-TSV (GS-TSV) equivalent electrical model with manufacturing faults is simulated and tested by using a multi-tone dither test signal, which is generated by modulating an RF signal with an optimized multi-tone signal. The peak-to-average ratio (PAR) is used as the test evaluation parameter to determine the type and size of the fault. The simulation results demonstrate the effectiveness of the multi-tone dither test method in the detection of voids (as low as ohm level) and pinholes (up to mega ohm level). It is obvious that this method performs better in the diagnosis of weak manufacturing faults in TSVs.

TSV Repair Architecture for Clustered Faults

The poor quality of the die stacking process for 3-D integrated circuits can result in the failure of the process in the through-silicon-vias (TSVs) in dense regions. Previous works use the same number of redundant TSVs and architectures that do not consider the TSV density. A repair architecture and an appropriate number of redundant TSVs, which are chosen considering the TSV density, are required for an improved repair rate. This paper proposes a method that demonstrates such an architecture and calculates the required number of TSVs. The method has a high repair rate for clustered faults, and wire-length problems are solved using the shift-based repair method.

Testing 3D-SoCs Using 2-D Time-Division Multiplexing

Through-silicon vias (TSVs) are used as high-speed vertical interconnects between dies in a 3-D system-on-a-chip (SoC). However, their speed cannot be exploited during test application due to inherent limitations of the scan-chains of the cores, which prevent the use of high shift frequencies during the scan-in/out operations. Moreover, due to their high area cost, only a limited number of TSVs can be utilized for test application. As a result, TSVs become the bottleneck for transferring the large volume of test-data to the various layers of the stack, and the time for testing the 3-D chip increases a lot. In this paper, we propose an efficient test-access mechanism (TAM) architecture that exploits the high speed of TSVs to minimize the time for testing 3-D SoCs. The proposed TAM architecture is based on a 2-D time-division-multiplexing approach, and by the means of a very effective test-scheduling method, it offers significant savings in test-time, TSV-count and TAM-cost under power and thermal constraints. Extensive experiments on two 3-D benchmark SoCs show the benefits of the proposed method.

An algorithm for obstacle‐avoiding clock routing tree construction with multiple TSVs on a 3D IC

Effective clock tree design is an important factor for determining chip performance. In this study, the authors present a 3D clock tree design algorithm to enhance the speed and performance of a VLSI chip. The authors propose an algorithm to determine the performance of the clock network by optimising both the clock skew and the dynamic power consumption of the 3D IC clock tree. The authors propose an algorithm for clock tree design based on the Elmore Delay method and routes all the sinks efficiently considering the obstacles with the use of an optimum number of through-silicon-vias (TSVs). The proposed method starts with a segregation technique to divide the sinks into smaller zones. Subsequently, an obstacle avoiding abstract clock tree is constructed with a minimum number of TSVs and buffers. The skew and dynamic power of the tree is calculated. Consequently, the proposed method is compared with recent existing works. The experimental results so obtained are quite encouraging.

Grouping-Based TSV Test Architecture for Resistive Open and Bridge Defects in 3-D-ICs

After the 3-D stacking, 3-D-ICs based on through-silicon-vias (TSVs) must be inspected for any TSV defects such as resistive open or bridge defects. In some research studies, several effective testing techniques have been developed such as parallel or serial test architectures, which measure the voltage across a single TSV with a comparator. However, in the current test architectures, hardware overhead and test time are proportional to the number of TSVs. In this paper, we propose a new unified test architecture for screening of TSV defects in 3-D-ICs. Depending on the number of assembled TSVs, the proposed grouping-based test architecture can effectively reduce the cumulative test time and hardware overhead without compromising the test quality.