Number Of Through-silicon Vias Research Articles

Fast Scan-Chain Ordering for 3-D-IC Designs Under Through-Silicon-Via (TSV) Constraints

This brief addresses the problem of scan-chain ordering under a limited number of through-silicon vias (TSVs), and proposes a fast two-stage algorithm to compute a final order of scan flip-flops. To enable 3-D optimization, a greedy algorithm, multiple fragment heuristic, is modified and combined with a dynamic closest-pair data structure, FastPair, to derive a good initial solution in stage one. Stage two initiates two local refinement techniques, 3-D planarization and 3-D relaxation, to reduce the wire (and/or power) cost and to relax the number of TSVs in use to meet TSV constraints, respectively. Experimental results show that the proposed algorithm results in comparable performance (in terms of wire cost only, power cost only, and both wire-and-power cost) to a genetic-algorithm method but runs two-order faster, which makes it practical for TSV-constrained scan-chain ordering for 3-D-IC designs.

Virtualized and fault-tolerant inter-layer-links for 3D-ICs

Through Silicon Via (TSV) is the state-of-the-art vertical interconnect technology in three dimensional Integrated Circuits (3D-ICs). TSVs offer short wire length with low capacitive load and, hence, fast connections between two or more chip layers. On the other hand, TSVs consume a relative large amount of chip area and are error prone during manufacturing resulting in a dramatic yield drop for large TSV counts. Because of their short wire length, TSVs can be clocked much higher than conventional intra-layer links. To efficiently utilize the vertical bandwidth of TSVs, this paper proposes multiplexing several virtual links with dynamically allocated bit rates for guaranteed service connections via a shared TSV-Hub-Array. Virtual links can be state-of-the-art interconnects like busses, crossbars or 2D-NoC links. The TSV-Hub allows migration of traditional 2D interconnects towards the 3D stack while benefiting from a reduced TSV count and reuse of existing IP blocks and interconnection schemes. Furthermore, the TSV-Hub approach is also advantageous under interconnect resilience considerations. An incorporated switchbox enables dynamic protection switching for several faulty TSVs. Moreover, it can even cope with situations when more than the number of spare TSVs becomes defective. By means of a case study with two independent AXI interconnects, we could show an area reduction in the range of at least 10% for a TSV size of 10μm and conservatively estimated the reliability improvement by one order of magnitude in comparison to a direct link interconnection.

Efficient routing techniques in heterogeneous 3D Networks-on-Chip

Abstract Three-dimensional Networks-on-Chips (3D NoCs) have recently been proposed to address the on-chip communication demands of future highly dense 3D multi-core systems. Homogeneous 3D NoC topologies have many Through Silicon Vias (TSVs) which have a costly and complex manufacturing process. Also, 3D routers use more memory and are more power hungry than conventional 2D routers. Alternatively, heterogeneous 3D NoCs combine both the area and performance benefits of 2D and 3D static router architectures by using a limited number of TSVs. To improve the performance of heterogeneous 3D NoCs, we propose an adaptive router architecture which balances the traffic in such NoCs. Particularly, experimental results show that our proposed architecture significantly improves the performance up to 75% by replacing 2D static routers with adaptive 2D routers in heterogeneous 3D NoCs, while keeping the maximum clock frequency, power and energy consumption of the adaptive router nearly at the same level as the static router.

Investigation of Local Bending Stress Effect on Complementary Metal–Oxide–Semiconductor Characteristics in Thinned Si Chip for Chip-to-Wafer Three-Dimensional Integration

A three-dimensional LSI (3D-LSI) that vertically stacks Si chips with a number of through-silicon vias (TSVs) and metal microbumps has attracted much attention recently. However, there are some issues to be resolved in the fabrication of 3D-LSI. In this study, we investigated impacts of local bending stress on the performance of a complementary metal–oxide–semiconductor (CMOS) circuit fabricated in a thinned Si chip. First, we proposed a novel method and a test structure to easily induce the local bending stress in the thinned Si chip. Then, we evaluated the distribution of the local bending stress and its effects on the electrical characteristics of metal–oxide–semiconductor field-effect transistor (MOSFETs). As a result, we observed the degradations of the MOSFET currents and CMOS inverter switching behaviors in accordance with the chip local bending. Our experimental results obviously indicate that the local bending stress caused large fluctuations in the performance of the circuit fabricated in the thinned Si chip.

TSV-Aware Analytical Placement for 3-D IC Designs Based on a Novel Weighted-Average Wirelength Model

Through-silicon vias (TSVs) are required for transmitting signals among different dies for the 3-D integrated circuit (IC) technology. The significant silicon areas occupied by TSVs bring critical challenges for 3-D IC placement. Unlike most published 3-D placement works that only minimize the number of TSVs during placement due to the limitations in their techniques, this paper proposes a new 3-D cell placement algorithm that can additionally consider the sizes of TSVs and the physical positions for TSV insertion during placement. The algorithm consists of three stages: 1) 3-D analytical global placement with density optimization and whitespace reservation for TSVs; 2) TSV insertion and TSV-aware legalization; and 3) layer-by-layer detailed placement. In particular, the global placement is based on a novel weighted-average (WA) wirelength model, giving the first published model that can outperform the well-known log-sum-exp wirelength model theoretically and empirically. Also, a scheme is proposed to enhance the numerical stability of the WA wirelength model. Furthermore, 3-D routing can easily be accomplished by traditional 2-D routers since the physical positions of TSVs are determined during placement. Experimental results show the effectiveness of our algorithm. Compared with state-of-the-art 3-D cell placement works, our algorithm can achieve the best routed wirelength, TSV counts, and total silicon area, in shortest running time.

An Analytical Placement Framework for 3-D ICs and Its Extension on Thermal Awareness

In this paper, we present a high-quality analytical 3-D placement framework. We propose using a Huber-based local smoothing technique to work with a Helmholtz-based global smoothing technique to handle the nonoverlapping constraints. The experimental results show that this analytical approach is effective for achieving tradeoffs between the wirelength and the through-silicon-via (TSV) number. Compared to the state-of-the-art 3-D placer ntuplace3d, our placer achieves more than 20% wirelength reduction, on average, with a similar number of TSVs. Furthermore, we extend this analytical 3-D placement framework with thermal awareness. While 2-D thermal-aware placement simply follows uniform power distribution to minimize temperature, we show that the same criterion does not work for 3-D ICs. Instead, we are able to prove that when the TSV area in each bin is proportional to the lumped power consumption of that bin and the bins in all tiers directly above it, the peak temperature is minimized. Based on this criterion, we implement thermal awareness in our analytical 3-D placement framework. Compared with a TSV oblivious method, which only results in an 8% peak temperature reduction, our method reduces the peak temperature by 34%, on average, with slightly less wirelength overhead. These results suggest that considering the thermal effects of TSVs is necessary and effective during the placement stage.

Deadlock-free generic routing algorithms for 3-dimensional Networks-on-Chip with reduced vertical link density topologies

3-Dimensional Networks-on-Chip (3D NoC) have emerged as the promising solution for scalability, power consumption and performance demands of next generation Systems-on-Chip (SoCs) interconnect. Due to the cost in terms of thermal, yield, chip area and design complexity, minimizing the number of Through-Silicon-Via (TSVs) in 3D ICs has become on the most important design issues. In this paper, we will present several stable, simple and deadlock-free generic routing algorithms for 3D NoCs with different reduced vertical link density topologies, which can maintain the 3D NoCs performance and save the system cost (TSV number, chip area, system power, etc.). The experimental results have been extracted from our cycle-accurate GSNOC simulator and have shown that our routing algorithms can maintain the system performance up to reducing 50% of TSVs number in comparison to the 100% TSVs number with ZXY routing algorithm configuration.

Elevator-First: A Deadlock-Free Distributed Routing Algorithm for Vertically Partially Connected 3D-NoCs

In this paper, we propose a distributed routing algorithm for vertically partially connected regular 2D topologies of different shapes and sizes (e.g., 2D mesh, torus, ring). The topologies that are the target of this algorithm are of practical interest in the 3D integration of heterogeneous dies using Through-Silicon-Vias (TSVs). Indeed, TSV-based 3D integration allows to envision the stacking of dies with different functions and technologies, using as an interconnect backbone a 3D-NoC. Intrinsically, 3D topologies have better performances, but yield and active area (and thus the cost) are function of the number of TSVs; therefore, the designs tend to use only a subset of available TSVs between two dies. The definition of blockage free and low implementation cost distributed deterministic routing on this kind of topology is thus of theoretical and practical interests. We formally prove that independently of the shape and dimensions of the planar topologies and of the number and placement of the TSVs, the proposed routing algorithm using two virtual channels in the plane is deadlock and livelock free. We also experimentally show that the performance of this algorithm is still acceptable when the number of vertical connections decreases.

TSV Minimization for Circuit — Partitioned 3D SoC Test Wrapper Design

Semiconductor technology continues advancing, while global on-chip interconnects do not scale with the same pace as transistors, which has become the major bottleneck for performance and integration of future giga-scale ICs. Three-dimensional (3D) integration has been proposed to sustain Moore’s law by incorporating through-silicon vias (TSVs) to integrate different circuit modules in the vertical direction, which is believed to be one of the most promising techniques to tackle the interconnect scaling problem. Due to its unique characteristics, there are many research opportunities, and in this paper we focus on the test wrapper optimization for the individual circuit-partitioned embedded cores within 3D System-on-Chips (SoCs). Firstly, we use existing 2D SoCs algorithms to minimize test time for individual embedded cores. In addition, vertical interconnects, i.e., TSVs that are used to construct the test wrapper should be taken into consideration as well. This is because TSVs typically employ bonding pads to tackle the misalignment problem, and they will occupy significant planar chip area, which may result in routing congestion. In this paper, we propose a series of heuristic algorithms to reduce the number of TSVs used in test wrapper chain construction without affecting test time negatively. It is composed of two steps, i.e., scan chain allocation and functional input/output insertion, both of which can reduce TSV count significantly. Through extensive experimental evaluations, it is shown that the test wrapper chain structure designed by our method can reduce the number of test TSVs dramatically, i.e., as much as 60.5 % reductions in comparison with the random method and 26 % in comparison with the intuitive method.

Power bumps and through‐silicon‐vias placement with optimised power mesh structure for power delivery network in three‐dimensional‐integrated circuits

Three-dimensional-integrated circuits (3D-ICs) bring new issues for power delivery network design because of larger current density and more complicated power delivery paths compared to 2D-IC. The power delivery network consists of power bumps, through-silicon-vias (TSVs), and power wires. IR-drop at each node varies with the number and position of power bumps and TSVs. These three power resources affect IR-drop of 3D-ICs. In this study, the authors propose power delivery network design methodology to optimise power resources wherease IR-drop constraint is satisfied. The simulation results show that the proposed method minimises the number of power bumps and TSVs compared to the conventional method.

Power Distribution in TSV-Based 3-D Processor-Memory Stacks

Three primary techniques for manufacturing through silicon vias (TSVs), via-first, via-middle, and via-last, have been analyzed and compared to distribute power in a 3-D processor-memory system with nine planes. Due to distinct fabrication techniques, these TSV technologies require significantly different design constraints, as investigated in this paper. A valid design space that satisfies the peak power supply noise while minimizing area overhead is identified for each technology. It is demonstrated that the area overhead of a 3-D power distribution network with via-first TSVs is approximately 9% as compared to less than 2% in via-middle and via-last technologies. Despite this drawback, a via-first based power network is typically overdamped and the issue of resonance is alleviated. A via-last based power network, however, exhibits a relatively low damping factor and the peak noise is highly sensitive to the number of TSVs and decoupling capacitance.

Cluster-based topologies for 3D Networks-on-Chip using advanced inter-layer bus architecture

Three-dimensional integrated circuits (3D ICs) have emerged as a viable candidate to achieve better performance and packaging density as compared to traditional two-dimensional (2D) ICs. In addition, combining the benefits of 3D ICs and Networks-on-Chip (NoCs) schemes provides a significant performance gain for 3D architectures. In recent years, through-silicon-via (TSV), employed for inter-layer connectivity (vertical channel), has attracted a lot of interest since it enables faster and more power efficient inter-layer communication across multiple stacked layers. The router-based and bus-based organizations are the two dominant architectures for utilizing TSVs as inter-layer communication channel in 3D architectures. Both approaches have some disadvantages. The former suffers from poor scalability and deteriorates the performance at high injection rates, and the latter consumes more area and power. The area overhead of TSVs reduces wafer utilization and yield, which can impact designing 3D architectures with a large number of TSVs. In this paper, two mesh-based topologies for 3D architectures are introduced to mitigate TSV footprint and power dissipation on each layer with a small performance penalty. On top of that, we propose a novel pipeline bus structure for inter-layer communication to improve the performance by reducing the delay and complexity of traditional bus arbitration.

3D-IC 전력 공급 네트워크를 위한 최적의 전력 메시 구조를 사용한 전력 범프와 TSV 최소화

3-dimensional integrated circuits (3D-ICs) have some problems for power delivery network design due to larger supply currents and larger power delivery paths compared to 2D-IC. The power delivery network consists of power bumps & through-silicon-vias (TSVs), and IR-drop at each node varies with the number and location of power bumps & TSVs. It is important to optimize the power bumps & TSVs while IR-drop constraint is satisfied in order to operate chip ordinarily. In this paper, the power bumps & TSVs optimization with optimized power mesh structure for power delivery network in 3D-ICs is proposed.

TSV Redundancy: Architecture and Design Issues in 3-D IC

3-D technology provides many benefits including high density, high bandwidth, low-power, and small form-factor. Through Silicon Via (TSV), which provides communication links for dies in vertical direction, is a critical design issue in 3-D integration. Just like other components, the fabrication and bonding of TSVs can fail. A failed TSV can severely increase the cost and decrease the yield as the number of dies to be stacked increases. A redundant TSV architecture with reasonable cost is proposed in this paper. Based on probabilistic models, some interesting findings are reported. First, the number of failed TSVs in a tier is usually less than 2 when the number of TSVs in a tier is less than 1000 and less than 5 when the number of TSVs in a tier is less than 10000. Assuming that there are at most 2-5 failed TSVs in a tier. With one redundant TSV allocated to one TSV block, our proposed structure leads to 90% and 95% recovery rates for TSV blocks of size 50 and 25, respectively. Finally, analysis on overall yield shows that the proposed design can successfully recover most of the failed chips and increase the yield of TSV to 99.4%.

Through-Silicon-Via Design with Clustering Structure and Adaptive Through-Silicon-Via Control for Three-Dimentional Solid-State-Drive Boost Converter System

This paper presents a through-silicon-via (TSV) design methodology for three-dimentional solid-state-drive (3D-SSD) system with the 20 V boost converter. Although TSV technologies give compact packaging and high performance compared to the conventional wire-bonding technology, the parasitic resistors and capacitors of TSVs may cause the performance degradation. Additionally, since the number of the activated NAND chip is dynamically changed as access patterns from real processor, the optimum design point for the boost converter is also moved according to the situation. Then, the clustering method with two different sizes of Cu-TSVs and the adaptive TSV number controlling technique for polycrystalline silicon TSVs are proposed to reduce the parasitic resistors and capacitors. With the cluster structure and Cu-TSVs, the performance of the proposed 3D-SSD is improved by ∼10%. Furthermore, the adaptive TSV number controller enhances the performance up to 2 times higher for poly-Si TSV case by reducing the parasitic elements due to TSVs.

Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs

Through-silicon via (TSV)-based 3-D stacked ICs (SICs) are becoming increasingly important in the semiconductor industry. In this paper, we address test architecture optimization for 3-D stacked ICs implemented using TSVs. We consider two cases, namely 3-D SICs with die-level test architectures that are either fixed or still need to be designed. We next present mathematical programming techniques to derive optimal solutions for the architecture optimization problem for both cases. Experimental results for three handcrafted 3-D SICs comprising of various systems-on-a-chip (SoCs) from the ITC'02 SoC test benchmarks show that compared to the baseline method of sequentially testing all dies, the proposed solutions can achieve significant reduction in test length. This is achieved through optimal test schedules enabled by the test architecture. We also show that increasing the number of test pins typically provides a greater reduction in test length compared to an increase in the number of test TSVs. Furthermore, we show that shorter test lengths are generally achieved with the larger, more complex dies lower in the stack. This is because test data must pass through every die lower in a stack in order to reach its target die, and with the larger dies lower in the stack, more test bandwidth may be provided to these dies using fewer routing resources.

3D NOC for many-core processors

With an increasing number of processors forming many-core chip multiprocessors (CMP), there exists a need for easily scalable, high-performance and low-power intra-chip communication infrastructure for emerging systems. In CMPs with hundreds of processing elements, 3D integration can be utilized to shorten long wires forming communication links. In this paper, we propose a Clos network-on-chip (CNOC) in conjunction with 3D integration as a viable network topology for many core CMPs. The primary benefit of 3D CNOC is scalability and a clear upper bound on power dissipation. We present the architectural and physical design of 3D CNOC and compare its performance with several other topologies. Comparisons are made among several topologies (fat tree, flattened butterfly, mesh and Clos) showing the power consumption of a 3D CNOC increases only minimally as the network size is scaled from 64 to 512 nodes relative to the other topologies. Furthermore, in a 512-node system, 3D CNOC consumes about 15% less average power than any other topology. We also compare 3D partitioning strategies for these topologies and discuss their effect on wire delay and the number of through-silicon vias.

Clock Tree synthesis for TSV-based 3D IC designs

For the cost-effective implementation of clock trees in through-silicon via (TSV)-based 3D IC designs, we propose core algorithms for 3D clock tree synthesis. For a given abstract tree topology, we propose DLE-3D ( d eferred l ayer e mbedding for 3D ICs), which optimally finds the embedding layers of tree nodes, so that the TSV cost required for a tree topology is minimized, and DME-3D ( d eferred m erge e mbedding for 3D ICs), which is an extended algorithm of the 2D merging segment, to minimize the total wirelength in 3D design space, with the consideration of the TSV effect on delay. In addition, when an abstract tree topology is not given, we propose NN-3D ( n earest n eighbor selection for 3D ICs), which constructs a (TSV and wirelength) cost-effective abstract tree topology for 3D ICs. Through experimentation, we have confirmed that the clock tree synthesis flow using the proposed algorithms is very effective, outperforming the existing 3D clock tree synthesis in terms of the number of TSVs, total wirelength, and clock power consumption.

Accurate TSV Number Minimization in High-Level Synthesis *

Recent progress in process technology makes it possible to vertically stack multiple integrated chips. In three dimensional integration circuits (3D ICs), through silicon vias (TSVs) are used to communicate signals between layers. However, TSVs act as obstacles during placement and routing and have a negative impact on chip yield. Therefore, TSV number minimization is an important topic in 3D IC design. However, previous high-level synthesis approach only tries to maximize the number of same-layer operation-level data- transfers. In fact, a TSV should correspond to a cross-layer resource-level data-transfer. Therefore, in this paper, we propose an integer linear programming (ILP) approach to per- form TSV number minimization by minimizing the number of cross-layer resource-level data-transfers. Experimental results consistently show that our approach is more effective than the previous approach in TSV number minimization.

Low-Power and Reliable Clock Network Design for Through-Silicon Via (TSV) Based 3D ICs

This paper focuses on low-power and low-slew clock network design and analysis for through-silicon via (TSV) based three-dimensional stacked ICs (3D ICs). First, we investigate the impact of the TSV count and the TSV resistance–capacitance (RC) parasitics on clock power consumption. Several techniques are introduced to reduce the clock power consumption and slew of the 3D clock distribution network. We analyze how these design factors affect the overall wire length, clock power, slew, and skew in 3D clock network design. Second, we develop a two-step 3D clock tree synthesis method: 1) 3D abstract tree generation based on the three-dimensional method of means and medians (3D-MMM) algorithm; 2) buffering and embedding based on the slew-aware deferred-merge buffering and embedding (sDMBE) algorithm. We also extend the 3D-MMM method (3D-MMM-ext) to determine the optimal number of TSVs to be used in the 3D clock tree so that the overall power consumption is minimized. Related SPICE simulation indicates that: 1) a 3D clock network that uses multiple TSVs significantly reduces the clock power compared with the single-TSV case, 2) as the TSV capacitance increases, the power savings of a multiple-TSV clock network decreases, and 3) our 3D-MMM-ext method finds a close-to-optimal design point in the “TSV count versus power consumption” tradeoff curve very efficiently.