Number Of Processors Research Articles

A Study on Parallel and Pipelining Simulation Techniques for Edge Detection and Their Performance Analysis

Real processing components along with component simulators are combined together to construct a new virtual prototyping system. The increase in component simulators result in degraded performance of the simulation in distributed systems. The speed of simulation can be increased by doing parallel simulation techniques. Prime number test and Image edge detection are chosen to implement the parallel simulation techniques and achieved the expected results while implementing in real time applications. The prime number test calculates the number of processors in a system and the image edge detection can be done in two stages by Canny Edge detection and Sobel Edge detection. The Canny Edge detection is used to detect the edges in the images by using a multi-stage algorithm. The smaller, separable and integer valued filter in images are combined in horizontal and vertical directions by using the Sobel edge detection resulting in reduction of implementation cost. The tool named OpenMP is used for implementing the parallel simulation techniques by combining both the canny edge and Sobel edge detection. An add-on named MPI is used along with the OpenMP to reduce the implementation time in parallel processing.

Performance Evaluation of Parallel International Data Encryption Algorithm on IMAN1 Super Computer

Distributed security is an evolving sub-domain of information and network security. Security applications play a serious role when data exchanging, different volumes of data should be transferred from one site to another safely and at high speed. In this paper, the parallel International Data Encryption Algorithm (IDEA) which is one of the security applications is implemented and evaluated in terms of running time, speedup, and efficiency. The parallel IDEA has been implemented using message passing interface (MPI) library, and the results have been conducted using IMAN1 Supercomputer, where a set of simulation runs carried out on different data sizes to define the best number of processor which can be used to manipulate these data sizes and to build a visualization about the processor number that can be used while the size of data increased. The experimental results show a good performance by reducing the running time, and increasing speed up of encryption and decryption processes for parallel IDEA when the number of processors ranges from 2 to 8 with achieved efficiency 97% to 83% respectively

A framework for parallel second order incremental optimization algorithms for solving partially separable problems

We propose Hessian Approximated Multiple Subsets Iteration (HAMSI), which is a generic second order incremental algorithm for solving large-scale partially separable convex and nonconvex optimization problems. The algorithm is based on a local quadratic approximation, and hence, allows incorporating curvature information to speed-up the convergence. HAMSI is inherently parallel and it scales nicely with the number of processors. We prove the convergence properties of our algorithm when the subset selection step is deterministic. Combined with techniques for effectively utilizing modern parallel computer architectures, we illustrate that a particular implementation of the proposed method based on L-BFGS updates converges more rapidly than a parallel gradient descent when both methods are used to solve large-scale matrix factorization problems. This performance gain comes only at the expense of using memory that scales linearly with the total size of the optimization variables. We conclude that HAMSI may be considered as a viable alternative in many large scale problems, where first order methods based on variants of gradient descent are applicable.

A Flexible Consensus Protocol for Distributed Systems

This paper presents a new type of Consensus problem named the Consensus (n, m) with alternative plans, where n denotes the total number of processors in the network, m is the number of processors with an initial value, n ≥ 4 and 1 ≤ m ≤ n. Compared to the traditional Consensus problem, the Consensus (n, m) problem with alternative plans has two major features. First, each processor is no longer required to propose an initial value. It can flexibly choose to propose or not propose an initial value. This feature allows the Consensus problem to be flexibly applied in many new real-world applications of the distributed system. Second, the proposed protocol ensures that all correct processors always agree on a good plan from a correct processor and never on a bad plan. Compared to solutions of the traditional Consensus problem, which does not guarantee that all correct processors agree on a good plan, this feature ensures the rationality of the Consensus value. In other words, by solving the Consensus (n, m) problem with alternative plans, the fault tolerance and reliability of distributed systems can be improved.

Towards Designing Asynchronous Microprocessors: From Specification to Tape-Out

Proceeding miniaturization in the VLSI circuits continues to pose challenges to the conventionally used synchronous design style in microprocessors. These include the distribution of clock in the GHz range, robustness to delay variations, reduction in electromagnetic interference, and energy conservation, to name a few. The asynchronous logic has been known for its ability to address the aforementioned challenges by means of the closed-loop handshake protocols, instead of notorious clock signals. Because of these advantages, there have been numerous attempts on building general and special purpose microprocessors during the last three decades. Still, however, the number of asynchronous processors commercially available is scarce, mainly due to an insufficient electronic design and automation tools support, an ambiguous design flow and testing mechanisms for asynchronous logic and, most importantly, absence of a forum to look for relevant works, explaining the design steps and tools for such microprocessors. This paper is intended to bridge this gap by 1) reviewing the design principles of asynchronous logic, including classification, signaling conventions, and pipelining approaches; 2) presenting the complete design flow and available electronic design and automation tools; 3) developing an encyclopedia of various general and special purpose microprocessors proposed by far; and 4) presenting an evaluation of those works in terms of area on the die and performance metrics. This paper will also serve as guidelines for the asynchronous microprocessor design and implementation in all phases from specification to tape-out.

Run-Time Resource Management Controller for Power Efficiency of GP-GPU Architecture

The demand for high-performance computing (HPC) has been increasing since the invention of computing technology. This led to the invocation of sophisticated multi/many-core processors with high performance. Graphical processing units (GPUs) have emerged as an important innovation in the many-core era as it features a high number of processors. The GPU acts as a computational accelerator that can significantly reduce the computational time of the HPC, as it can offer standout parallelism for high-end computing applications such as graphics designing. However, increasing the resources has resulted in higher power consumption and heat dissipation which has been a challenging problem for modern HPC Units. On the other hand, because of the dynamic nature of workload, a large amount of parallelism, offered by these many-core processors, is often underutilized. An ideal system would be smart enough to efficiently utilize resources and save power where less workload is available. Reducing the resources dynamically has direct implications on the performance of the system. However, if less workload is available, reducing the resources would not harm the performance, rather it would save power with less to no trade-off in overall throughput of the system. In this paper, a smart power and performance efficient resource management controller for general purpose-GPU architecture is presented. The proposed controller, based on a feedback mechanism, keeps on analyzing the current frequency of central processing unit (CPU) and GPU, number of active cores of the CPU and utilization of CPU and GPU. On the basis of collected data, the proposed controller which features fuzzy type-2 as an optimizing mechanism tries to create a balance between performance and power consumption. The results are evaluated against various benchmarks on NVIDIA TK1 GPU kit and by using dynamic voltage and frequency scaling and core gating, up to 47 % reduction in power consumption has been achieved.

A Low Power Consuming Model of Parallel Programming for HPC System

For most of the past five decades, the growing computational power of supercomputers has come primarily from a doubling of clock frequency every 18 months. Over this time period, the clock rate increased by six orders of magnitude, while the number of processors increased by three orders of magnitude. The major challenge caused by the increasing scale and complexity of HPC systems is the massive power consumption. Due to constraints on heat and the power requirements of today's microprocessors, vendors have shifted to putting multiple processors (cores) on a chip. The number of cores per chip is expected to continue increasing exponentially over the next decade. One expected strategy is the correct usage of parallel programming models that decrease power consumption and increase system performance through massive parallelism (concurrency). In the current study, we have proposed a Hybrid MVAPICH-2 + CUDA (HMC) parallel programming model that outperformed other state-of-the-art dual and tri hierarchy level approaches with respect to power consumption and execution time. Moreover, the HMC model was evaluated by implementing the matrix multiplication benchmarking application. Consequently, it can be considered a leading model for the emerging Exascale computing system.

A parallel domain decomposition algorithm for large scale image denoising

Total variation denoising (TVD) is an effective technique for image denoising, in particular, for recovering blocky, discontinuous images from noisy background. The problem is formulated as an optimization problem in the space of bounded variation functions, and the solution is obtained by solving the associated Euler–Lagrange equation defined on the domain occupied by the entire image. The method offers high quality results, but is computationally expensive for large images, especially for three-dimensional problems. In this paper, we introduce a highly parallel version of the algorithm which formulates the problem as multiple overlapping, but independent, optimization problems, and each is defined on a portion of the image domain. This approach is similar to the overlapping Schwarz type domain decomposition method, but is non-iterative, for solving partial differential equations, and is highly scalable, without using any coarse grids, for parallel computers with a large number of processors. We show by a theory and also by some two- and three-dimensional numerical experiments that the new approach has similar numerical accuracy as the classical TVD approach, but is much more efficient on parallel computers.

Parallel construction of binary tree based on sorting

Introduction. Algorithms for the parallel binary tree construction are developed. The algorithms are based on sorting and described in a constructive form. For the Nelement set, the time complexity has T(R) = O(1) and T(R) = O(log2 N) estimates, where R = (N2-N)/2 is the number of processors. The tree is built with the uniqueness property. The algorithms are invariant with respect to the input sequence type. The work objective is to develop and study ways of accelerating the process of organizing and transforming the tree-like data structures on the basis of the stable maximum parallel sorting algorithms for their application to the basic operations of information retrieval on databases.Materials and Methods. A one-to-one relation between the input element set and the binary tree built for it is established using a stable address sorting. The sorting provides maximum concurrency, and, in an operator form, establishes a one-to-one mapping of input and output indices. On this basis, methods for the mutual transformation of the binary data structures are being developed.Research Results. An efficient parallel algorithm for constructing a binary tree based on the address sorting with time complexity of T(N2) = O(log2 N) is obtained. From the well-known analogues, the algorithm differs in structure and logarithmic estimation of time complexity, which makes it possible to achieve the acceleration of O(Nα), α≥1 order analogues. As an advanced version, an algorithm modification, which provides the maximum parallel construction of the binary tree based on a stable address sorting and a priori calculation of the stored subtree root indices is suggested. The algorithm differs in structure and estimation of T(1) = O(1) time complexity. A similar estimate is achieved in a sequential version of the modified algorithm, which allows obtaining the acceleration of known analogs O(Nα), α>1 order.Discussion and Conclusions. The results obtained are focused on the creation of effective methods for the dynamic database processing. The proposed methods and algorithms can form an algorithmic basis for an advanced deterministic search on the relational databases and information systems.

Non-clairvoyant scheduling with conflicts for unit-size jobs

We consider the problem of scheduling unit-size jobs with conflicts in a non-clairvoyant setting. In this problem, all jobs are released at the same time but the conflict graph is unknown to the scheduling algorithm beforehand. Instead, the conflicts between the jobs are revealed online by an adversary during the jobs' execution. There is an unlimited number of processors so that all jobs could be executed simultaneously. However, two jobs with a conflict cannot be both completed in the same time step; when their conflict is revealed, one of them must be aborted and re-executed later. The objective is to minimize the total number of time steps required to complete all jobs, or the makespan. We present an online non-clairvoyant algorithm and analyze its performance for three types of conflict graphs. For bipartite graphs, we show that it is O(log⁡n)-competitive, where n denotes the total number of jobs. For unit-interval graphs, we show that it is O(log⁡χ)-competitive, where χ denotes the chromatic number of the graph. For bounded-degree graphs, we show that it is O(Δ)-competitive, where Δ denotes the maximum degree of any node in the graph. For bipartite and bounded-degree graphs, we also provide matching lower bounds and show that the obtained competitive ratios are asymptotically tight.

Cost-efficient parallel processing of irregularly structured problems in cloud computing environments

In this paper, we deal with optimizing the monetary costs of executing parallel applications in cloud-based environments. Specifically, we investigate on how scalability characteristics of parallel applications impact the total costs of computations. We focus on a specific class of irregularly structured problems, where the scalability typically depends on the input data. Consequently, dynamic optimization methods are required for minimizing the costs of computation. For quantifying the total monetary costs of individual parallel computations, the paper presents a cost model that considers the costs for the parallel infrastructure employed as well as the costs caused by delayed results. We discuss a method for dynamically finding the number of processors for which the total costs based on our cost model are minimal. Our extensive experimental evaluation gives detailed insights into the performance characteristics of our approach.

Accelerating single molecule localization microscopy through parallel processing on a high-performance computing cluster.

SummarySuper‐resolved microscopy techniques have revolutionized the ability to study biological structures below the diffraction limit. Single molecule localization microscopy (SMLM) techniques are widely used because they are relatively straightforward to implement and can be realized at relatively low cost, e.g. compared to laser scanning microscopy techniques. However, while the data analysis can be readily undertaken using open source or other software tools, large SMLM data volumes and the complexity of the algorithms used often lead to long image data processing times that can hinder the iterative optimization of experiments. There is increasing interest in high throughput SMLM, but its further development and application is inhibited by the data processing challenges. We present here a widely applicable approach to accelerating SMLM data processing via a parallelized implementation of ThunderSTORM on a high‐performance computing (HPC) cluster and quantify the speed advantage for a four‐node cluster (with 24 cores and 128 GB RAM per node) compared to a high specification (28 cores, 128 GB RAM, SSD‐enabled) desktop workstation. This data processing speed can be readily scaled by accessing more HPC resources. Our approach is not specific to ThunderSTORM and can be adapted for a wide range of SMLM software.Lay DescriptionOptical microscopy is now able to provide images with a resolution far beyond the diffraction limit thanks to relatively new super‐resolved microscopy (SRM) techniques, which have revolutionized the ability to study biological structures. One approach to SRM is to randomly switch on and off the emission of fluorescent molecules in an otherwise conventional fluorescence microscope. If only a sparse subset of the fluorescent molecules labelling a sample can be switched on at a time, then each emitter will be, on average, spaced further apart than the diffraction‐limited resolution of the conventional microscope and the separate bright spots in the image corresponding to each emitter can be localised to high precision by finding the centre of each feature using a computer program. Thus, a precise map of the emitter positions can be recorded by sequentially mapping the localisation of different subsets of emitters as they are switched on and others switched off.Typically, this approach, described as single molecule localisation microscopy (SMLM), results in large image data sets that can take many minutes to hours to process, depending on the size of the field of view and whether the SMLM analysis employs a computationally‐intensive iterative algorithm. Such a slow workflow makes it difficult to optimise experiments and to analyse large numbers of samples. Faster SMLM experiments would be generally useful and automated high throughput SMLM studies of arrays of samples, such as cells, could be applied to drug discovery and other applications. However, the time required to process the resulting data would be prohibitive on a normal computer.To address this, we have developed a method to run standard SMLM data analysis software tools in parallel on a high‐performance computing cluster (HPC). This can be used to accelerate the analysis of individual SMLM experiments or it can be scaled to analyse high throughput SMLM data by extending it to run on an arbitrary number of HPC processors in parallel. In this paper we outline the design of our parallelised SMLM software for HPC and quantify the speed advantage when implementing it on four HPC nodes compared to a powerful desktop computer.

Fully Flexible Parallel Merge Sort for Multicore Architectures

The development in multicore architectures gives a new line of processors that can flexibly distribute tasks between their logical cores. These need flexible models of efficient algorithms, both fast and stable. A new line of efficient sorting algorithms can support these systems to efficiently use all available resources. Processes and calculations shall be flexibly distributed between cores to make the performance as high as possible. In this article we present a fully flexible sorting method designed for parallel processing. The idea we describe in this article is based on modified merge sort, which in parallel form is designed for multicore architectures. The novelty of this idea is in particular way of processing. We have developed a fully flexible method that can be implemented for a number of processors. The tasks are flexibly distributed between logical cores to increase the efficiency of sorting. The method preserves separation of concerns; therefore, each of the processors works separately without any cross actions and interruptions. The proposed method was described in theoretical way, examined in tests, and compared to other methods. The results confirm high efficiency and show that with each newly added processor sorting becomes faster and more efficient.

Multigrid treatment of implicit continuum diffusion

Implicit treatment of diffusive terms of various differential orders common in continuum mechanics modeling, such as computational fluid dynamics, is investigated with spectral and multigrid algorithms in non-periodic 2D domains. In doubly periodic time dependent problems these terms are handled efficiently by spectral methods, but in non-periodic systems solved with distributed memory parallel computing and 2D domain decomposition, this efficiency is lost for a large number of processors. We built and present here a multigrid algorithm for these types of problems that outperforms a spectral solution employing the highly optimized FFTW library. This solver is suitable for high performance computing and may be able to efficiently treat implicit diffusion of arbitrary order by introducing auxiliary equations of lower order. We test these solvers for fourth and sixth order diffusion with harmonic test functions as well as turbulent 2D magnetohydrodynamic simulations. It is also shown that an anisotropic operator without mixed-derivative terms improves model accuracy and speed, and we examine the impact that the various diffusion operators have on the energy, the enstrophy, and the qualitative aspect of a simulation.

Post-Quantum Key Exchange on ARMv8-A: A New Hope for NEON Made Simple

NewHope and NewHope-Simple are two recently proposed post-quantum key exchange protocols based on the hardness of the Ring-LWE problem. Due to their high security margins and performance, there have already been discussions and proposals for integrating them into Internet standards, like TLS, and anonymity network protocols, like Tor. In this work, we present constant-time and vector-optimized implementations of NewHope and NewHope-Simple for ARMv8-A 64-bit processors which target high-speed applications. This architecture is implemented in a growing number of smart phone and tablet processors, and features powerful 128-bit SIMD operations provided by the NEON engine. In particular, we propose the use of three alternative modular reduction methods. They allow to better exploit NEON parallelism by avoiding larger data types during the Number Theoretic Transform ( $\sf{NTT}$ ). Furthermore, they remove the need to transform input coefficients into Montgomery domain during pointwise multiplications. The NEON vectorized $\sf{NTT}$ uses a 16-bit unsigned integer representation and executes in only 18,909 clock cycles on an ARM Cortex-A53 core. Our implementation improves previous assembly-optimized results on ARM NEON platforms and outperforms the C reference implementation on the same platform by a factor of 8.3. The total time spent on the key exchange was reduced by more than a factor of 3.5 for both protocols.

Resource Optimization for Real-Time Streaming Applications Using Task Replication

In this paper, we study the problem of exploiting parallelism in a hard real-time streaming application modeled as an acyclic synchronous data flow (SDF) graph and scheduled on a heterogeneous multiprocessor system-on-chip platform to alleviate the capacity fragmentation due to partitioned scheduling algorithms and reduce the number of required processors when a throughput requirement is satisfied. As the main contribution in this paper, we propose a method to determine a replication factor for each task in an acyclic SDF graph such that by distributing the workloads among more parallel tasks with lower utilization in the obtained transformed graph, the left capacity on the processors can be efficiently exploited, hence reducing the number of required processors. The experimental results, on a set of real-life streaming applications, demonstrate that our approach can reduce the minimum number of processors required to schedule an application and considerably improve the memory requirements and application latency compared to related approaches while meeting the same throughput constraint.

A high expansion implicit finite-element prestack reverse time migration method

Building on the concepts of cohesion degree and local relaxation, we propose an integrated hierarchical equilibrium parallel finite-element reverse time migration (HEP-FE-RTM) algorithm, which is a fine-grained central processing unit (CPU) parallel computation method in two-level host-sub-processors mode. A single master process is responsible for data reading and controlling the progress of the calculation, while each subordinate process deals with a part of the depth domain space. This algorithm is able to achieve single source forward-modelling and inversion calculation using more than 2000 CPUs. On the premise of controlling iteration times for convergence, sub-module/processors only communicate with their adjacent counterparts and the host processor, so the level of data exchange is proportional to cohesion degree. This HEP-FE-RTM algorithm has the distinct advantage that parallel efficiency does not decrease as the number of processors increases. In two-level host-sub-processors mode, more than 2000 processors are used and one billion unknowns are solved. By combining the finite-element implicit dynamic Newmark integral scheme, this approach achieves a prestack reverse time migration (RTM) with high expansion. Making full use of the characteristics of high accuracy and strong boundary adaptability of the finite-element method, through the optimisation of finite-element solving, the HEP-FE-RTM algorithm improved the efficiency of parallel computing and achieved RTM implementation using finite element. Model tests show that this method has a significant effect on both imaging efficiency and accuracy.

On parallel computation of centrality measures of graphs

Centrality measures or indicators of centrality identify most relevant nodes of graphs. Although optimized algorithms exist for computing of most of them, they are still time consuming and are even infeasible to apply to big enough graphs like the ones representing social networks or extensive enough computer networks. In this paper, we present a parallel implementation in C language of some optimal algorithms for computing of some indicators of centrality. Our parallel version greatly reduces the execution time of their sequential (non-parallel) counterpart. The proposed solution relies on threading, allowing for a theoretical improvement in performance close to the number of logical processors (cores) of the single computer in which it is running. Our software has been tested in several platforms, including the supercomputer Calendula, in which we achieved execution times close to 18 times faster when running our parallel implementation instead of our sequential one. Our solution is multi-platform and portable, working on any machine with several logical processor which is capable of compiling and running C language code.

A parallel branch-and-bound algorithm to compute a tighter tardiness bound for preemptive global EDF

In this paper we present a parallel exact algorithm to compute an upper bound to tardiness of preemptive global EDF (G-EDF) schedulers, named harmonic bound, which has been proved to be up to 30% tighter than previously proposed bounds. Tightness is a crucial property of tardiness bounds: a too loose bound may cause a feasible soft real-time application to be mistakenly deemed unfeasible. Unfortunately, no polynomial-time algorithm is known to date to compute the harmonic bound. Although there is no proof of hardness of any sort either, the complex formula of the bound apparently provides no hints to devise algorithms with sub-exponential worst-case cost. In this paper we address this issue by proposing a parallel, exact, branch-and-bound algorithm to compute the harmonic bound, called harm-BB, which proves to be extremely fast in a large number of experiments. More specifically, we compare its execution times with those of existing polynomial-time algorithms for other known tardiness bounds on 630,000 random task sets. harm-BB outperforms, or is comparable to, the competitor algorithms in all scenarios but the ones with the highest number of processors (7 and 8) and tasks ( $$\sim $$ 50). In the latter scenarios harm-BB is indeed slower than the other algorithms; yet, it was still feasible, as it takes only about 2.8 s to compute the bound on a commodity dual-core CPU. Even better, we show that harm-BB has a high parallel efficiency, thus its execution time may be largely cut down on highly-parallel platforms.

Моделирование развития вихревых структур в сверхзвуковом газовом потоке

With the help of mathematical modeling methods we studied the evolution of whirl structures moving in a gas behind a shock wave front. This shock wave is defined by the Hugoniot relations. The Hugoniot relations allow finding the parameters of the gas behind the shock wave front, if the Mach number and gas parameters before the pressure jump are known. We developed a parallel algorithm and a numerical code for solving 2D gas dynamics equations. We made numerical simulations that modeled the shock wave interaction with whirl structures of different configurations (single whirl, two whirls with different directions of their vectors). We demonstrated the results of test simulations in a supercomputer with a different number of processors. It was shown that using 40 processors allows decreasing the duration of a test simulation approximately by the factor of 30. We described the results of the calculation of interaction of one/two whirls with the incident wave and the reflected waves. The gas dynamics parameters at the moment t = 0 were set with the help of Bernoulli law. Besides, we made a comparison with a similar program based on another algorithm (particle-in-cell method). It was shown that the interaction of two whirls with opposite directions does not lead to their compensation, but the interaction area (turbulent zone) has a complicated shape. The possibility of natural experiments with the help of a shock tube and a laser shock tube is discussed in the article. Such research would allow comparing the experimental data with the results of numerical simulations and developing more complicate models of the turbulent motion.