Number Of Metal Layers Research Articles

M5X4: A Family of MXenes.

MXenes are two-dimensional (2D) transition metal carbides, nitrides, and carbonitrides typically synthesized from layered MAX-phase precursors. With over 50 experimentally reported MXenes and a near-infinite number of possible chemistries, MXenes make up the fastest-growing family of 2D materials. They offer a wide range of properties, which can be altered by their chemistry (M, X) and the number of metal layers in the structure, ranging from two in M2XTx to five in M5X4Tx. Only one M5X4 MXene, Mo4VC4, has been reported. Herein, we report the synthesis and characterization of two M5AX4 mixed transition metal MAX phases, Ti2.5Ta2.5AlC4 and Ti2.675Nb2.325AlC4, and their successful topochemical transformation into Ti2.5Ta2.5C4Tx and Ti2.675Nb2.325C4Tx MXenes. The resulting MXenes were delaminated into single-layer flakes, analyzed structurally, and characterized for their thermal and optical properties. This establishes a family of M5AX4 MAX phases and their corresponding MXenes. These materials were experimentally produced based on guidance from theoretical predictions, leading to more exciting applications for MXenes.

Ordered Double Transition Metal MXenes

AbstractSince the discovery of MXenes, research has progressed tremendously to explore MXenes with new compositions apart from the conventional Ti3C2Tx. Recently, the MXene family further expanded with the discovery of ordered double transition metal MXenes, wherein the metal sites are occupied by two different transition metals, which can be arranged in‐plane or out‐of‐plane forming i‐MXenes or o‐MXenes, respectively. The feature of optimizing the properties of ordered double transition metal MXenes by precise engineering of the composition, number of metal layers, interlayer spacing, and surface functionalities is distinctive among the existing 2D materials. This review provides a brief overview of the theoretical and experimental studies on the ordered double transition metal MXenes to elucidate its structure and properties. In addition, the recent trends in the synthesis and the effects of fine‐tuning the composition, structure, and functional groups on their electrochemical performance are elaborated. The current challenges faced by these emerging MXenes and future research directions are also proposed.

Interconnect Technology/System Co-Optimization for Low-Power VLSI Applications Using Ballistic Materials

Promising interconnect materials continue to emerge and are considered as potential replacements for Cu interconnects. In this article, an interconnect technology/system codesign methodology is presented to efficiently optimize generic interconnects using ballistic materials. The key requirements of material-level characteristics to replace conventional Cu counterparts are quantified, such as the channel density, mean free path (MFP), and contact resistance. Furthermore, to achieve maximal chip-level throughput, two interconnect design schemes are proposed and optimized under a given number of metal layers, die area, and power density constraints. Results demonstrate that the optimal design scheme strongly depends on the power constraint, driving devices as well as material parameters, including the contact resistance. It is shown that up to 45% of the throughput improvement can be achieved by replacing both local and intermediate Cu interconnects at an ultralow-power budget.

$4\times8$ Patch Array-Fed FR4-Based Transmit Array Antennas for Affordable and Reliable 5G Beam Steering

This paper presents a novel method of designing affordable 28-GHz transmit array antennas utilizing FR4 substrates, which are low-cost but lossy. It is demonstrated that low insertion loss can be achieved by employing appropriate combinations of spatial filter unit cells, where each unit cell is selected to minimize the loss factors defined by lossy spatial filter modeling. The loss factor with inter-layer couplings was found to be more variable than that without inter-layer couplings, although inter-layer couplings have previously been utilized to increase the tunable range of the phase shift. Therefore, the number of metal layers in the low-pass spatial filter more affected by the inter-layer coupling is selected to be less than the number of metal layers used in the bandpass spatial filter for a given thickness in the proposed method. In addition, a novel transmits array in which some of the unit cells are sinusoidally arranged is described. This can achieve up to 1.6-dB gain enhancement at some steered angles compared with the conventional design. To simulate transmit arrays rapidly, an effective simple medium structure representing a transmit array is presented. Finally, the measured results confirm the effectiveness of the proposed design approaches for affordable transmit array antennas. Only a small difference of 0.8 dB between the simulated and measured results confirms the successful manipulation of the lossy characteristic of FR4.

Effect of Stacking Sequence on Low-Velocity Impact Behavior of Metal Laminates

In this paper, the low-velocity impact behavior of metal laminates was studied experimentally and numerically. Metal laminates with different number of metal layers and different stacking sequences were investigated by examining the contact force, the contact duration, the dissipated energy and the transverse displacement as the main low-velocity impact responses. It was found that from stacking sequence perspective, the low-velocity impact responses of metal laminates were mainly affected by the volume fraction of metal layers, the material characteristics of the first and last metal layers and the number of metal layers. Increasing the number of metal layers in a constant thickness of metal laminates decreased the contact force and increased the contact duration and transverse displacement. The use of higher volume fraction of a metal material in a metal laminate caused the metal laminate to inherit more of the impact characteristics of that material. The results of this research can assist engineers to design metallic structures with desired low-velocity impact behaviors.

Silver-Sulfur Hybrid Supertetrahedral Clusters: The Hitherto Missing Members in the Metal-Chalcogenide Tetrahedral Clusters.

The synthesis of Group 11 metal chalcogenide supertetrahedral clusters (SCs) still remains a great challenge mainly due to the high tendency of metal aggregation through metallophilicity and global charge balance. Demonstrated herein are the preparation, crystallographic characterization, and optical properties of two stable silver-sulfur SCs through ligand-control; one as a discrete zero-dimensional (0D) V3,4-type cluster and the other as a one-dimensional (1D) zigzag chain extended by alternating V3,2-type clusters. The notation Vn,m (where n is the number of metal layers, and m is the number of vacant corners) is used to describe a new series of vacant-corner SCs, which can be derived from the regular Tn clusters. The existence of vacant-corner-type SCs may be ascribed to the low valence and tri-coordinated environment of silver ions. These are the first representatives of structurally determined silver-sulfur tetrahedral clusters thus far. This work enriches the coinage-metal chalcogenide tetrahedral cluster portfolio, discovers vacant-corner SCs present in silver-sulfur hybrid tetrahedral clusters, and provides effective means for further development of Group 11 coinage-metal chalcogenide SCs.

Two-Dimensional MXenes as Catalysts for Electrochemical Hydrogen Evolution: A Computational Screening Study

We use density functional theory calculations to explore different polymorphs of a new class of 2D materials commonly known as MXenes, which are primarily carbides and nitrides of transition metals. The stability of the M2X, M3X2, and M4X3 polymorphs in their bare and functionalized forms is assessed via the calculated standard heat of formation. We find that most of the MXenes are metallic, and we investigate their performance as electrocatalysts for the hydrogen evolution reaction (HER) using the free energy of hydrogen adsorption at equilibrium coverage as an activity descriptor. For a given type of metal, we find that the hydrogen adsorption energy can vary by up to 0.5 eV depending on the number of metal layers in the structure, suggesting that the catalytic activity of MXenes can be tuned by controlling the layer thickness. On the basis of a combined stability and activity analysis of 72 different MXenes, we identify several new promising nonprecious HER electrocatalysts.

Theoretical analysis of structures and electronic spectra in molecular cadmium chalcogenide clusters.

We present calculated structural and optical properties of molecular cadmium chalcogenide nonstoichiometric clusters with a size range of less than 1 nm to more than 2 nm with well-defined chemical compositions and structures in comparison to experimental characterization and previous theoretical work. A unified treatment of these clusters to obtain a fundamental understanding of the size, ligand, and solvation effects on their optical properties has not been heretofore presented. The clusters belong to three topological classes, specifically supertetrahedral (Tn), penta-supertetrahedral (Pn), and capped supertetrahedral (Cn), where n is the number of metal layers in each cluster. The tetrahedrally shaped Tn clusters examined in this work are Cd(ER)4(2-) (T1), Cd4(ER)10(2-) (T2), and Cd10E4 (')(ER)16(4-) (T3), where R is an organic group, E and E' are chalcogen atoms (sulfur or selenium). The first member of the Pn series considered is M8E'(ER)16(2-). For the Cn series, we consider the first three members, M17E4 (')(ER)28(2-), M32E14 (')(ER)36L4, and M54E32 (')(ER)48L4(4-) (L = neutral ligand). Mixed ligand clusters with capping ER groups replaced by halogen or neutral ligands were also considered. Ligands and solvent were found to have a large influence on the color and intensity of the electronic absorption spectra of small clusters. Their effects are generally reduced with increasing cluster sizes. Blueshifts were observed for the first electronic transition with reduced size for both cadmium sulfide and cadmium selenide series. Due to weakly absorbing and forbidden transitions underlying the one-photon spectra, more care is needed in interpreting the quantum confinement from the clusters' lowest-energy absorption bands.

Ternary Borides Cr2AlB2, Cr3AlB4, and Cr4AlB6: The First Members of the Series (CrB2)nCrAl with n = 1, 2, 3 and a Unifying Concept for Ternary Borides as MAB-Phases.

Single crystals of the ternary borides Cr2AlB2, Cr3AlB4, Cr4AlB6, MoAlB, WAlB, Mn2AlB2, and Fe2AlB2 were grown from the elements with an excess of Al. Structures were refined by X-ray methods on the basis of single crystal data. All compounds crystallize in orthorhombic space groups. In each case boron atoms show the typical trigonal prisms BM6. The BM6-units are linked by common rectangular faces forming B-B-bonds. Thus, zigzag chains of boron atoms are obtained for MoAlB, WAlB, and M2AlB2 (M = Cr, Mn, Fe); chains of hexagons for Cr3AlB4; and double chains of hexagons for Cr4AlB6. The same subunits are known for the binary borides CrB, Cr3B4, Cr2B3, and β-WB, too. The boride partial structures are separated by single layers of Al-atoms in the case of the chromium compounds and double layers for WAlB, i.e., W2Al2B2. All crystal structures can be described using a unified building set principle with quadratic 4(4)-nets of metal atoms. The different compositions and crystal structures are obtained by different numbers of metal layers in the corresponding parts according to the formula (MB)2Aly(MB2)x. This principle is an extension of a scheme which was developed for the boridecarbides of niobium. Furthermore, there is a close similarity to the group of ternary carbides MAl(MC)n, so-called MAX-phases. Therefore, they might be named as "MAB-phases". The pronounced two-dimensionality and the mixture of strong covalent and metallic interactions make MAB-phases to promising candidates for interesting material properties. All compositions were confirmed by EDX measurements. Additionally, microhardness measurements were performed.

Effects of mechanical and geometrical properties of adhesive and metal layers on low-velocity impact behavior of metal laminate structures

In this study, the effects of mechanical and geometrical properties of the adhesive layers and mechanical properties of the metal layers on low-velocity impact behavior of adhesively bonded metal laminates (ABML) were investigated. The contact force, the transverse displacement, the contact duration, and the dissipated energy were considered as the main structure responses under impact loading. To study the effects of mechanical and geometrical properties of adhesive layers on low-velocity impact behavior of ABML, two different adhesive materials and two different adhesive thicknesses were considered. The results showed that the contact force was more depended on the adhesive thickness and nearly unaffected by the adhesive material, whereas the dissipated energy was more depended on the adhesive material rather than the adhesive thickness in case the overall structure thickness was remained fixed. To determine the effects of material parameters of the metal layers including the yield stress, the elastic modulus, the density, and the tangent modulus on the impact behavior of ABML, finite element analyses were carried out. The results showed that increasing the number of metal layers in a constant total thickness caused decrease of the total contact force and increase of the contact duration and transverse displacement of the structure due to more widespread plastic deformation occurred in the layers. The material yield stress and Young’s modulus were the most influencing material parameters on the mechanical behavior of ABML under low-velocity impact loading. The finite element models were well validated against the experimental and numerical results.

Multispectral optical enhanced transmission of a continuous metal film coated with a plasmonic core-shell nanoparticle array

We propose and show multispectral optical enhanced transmission in the visible and near-infrared region in a continuous metal film coated with a two-dimensional (2D) hexagonal non-close-packed plasmonic array. The plasmonic array consists of metal/dielectric multilayer core-shell nanoparticles. The excitation of near-field plasmon resonance coupling between adjacent core-shell nanoparticles, plasmon resonance coupling between adjacent metal layers in the nanoparticle, and surface plasmon (SP) waves on the metal film are mainly responsible for the multispectral optical enhanced transmission behavior. The multispectral optical enhanced transmission response could be highly modified in the wavelength range, transparent bandwidth and transmission intensity by varying the geometry parameters including the gap distance between adjacent plasmonic nanoparticles, the size of metal core and the thickness of dielectric layer between the metal layers. In addition, the number of optical enhanced transmission bands increases with the number of metal layers in the plasmonic nanoparticle. The proposed structure shows many merits such as the deep sub-wavelength size, multispectral optical enhanced transmission bands as well as fully retained electric and mechanical properties of the natural metal. These merits may provide promising applications for highly integrated optoelectronic devices including plasmonic filters, nanoscale multiplexers, and nonlinear optics.

Coupling of Surface Plasmons and Excited Optical Modes in Metal/Dielectric Grating Stacks

In this work, we investigate the coupling of surface plasmons and excited optical modes in metal/dielectric grating stacks theoretically and experimentally. We have observed three kinds of modes in these structures: the cavity mode, the propagated surface plasmon (PSP) mode and the localized surface plasmon (LSP) mode, which can enhance the optical transmission. Firstly, it is shown that the cavity mode is excited in the grating stacks. And the cavity mode has redshift if we enhance the thickness of metal layers, while it has blueshift when we increase the thickness of dielectric layers. The redshift of the cavity mode also occurs when the number of repeating layers is increased. Secondly, the PSP mode is also excited, which can be described by the effective permittivity method. It is found that the PSP modes are coupled with each other, which leads to a modified dispersion relation of surface plasmon polaritons (SPP). The theoretical analysis is in good agreement with the observed transmission enhancement in the grating stacks. And the coupling of PSPs also leads to a blueshift when the number of metal layers is increased. Thirdly, the LSP mode, generated in single metal strip, can also enhance the optical transmission of the grating stacks. Yet the transmission intensity induced by LSP decreases rapidly with increasing the number of metal layers. The investigations here may have potential applications in designing plasmonic metamaterials and subwavelength optical devices.

A Fully Polynomial-Time Approximation Scheme for Timing-Constrained Minimum Cost Layer Assignment

As VLSI technology enters the nanoscale regime, the interconnect delay becomes the bottleneck of circuit performance. Compared with gate delays, wires are becoming increasingly resistive, making it more difficult to propagate signals across the chip. However, more advanced technologies (65 and 45 nm) provide relief as the number of metal layers continues to increase. The wires on the upper metal layers are much less resistive and can be used to drive further and faster than on thin metals. This provides an entirely new dimension to the traditional wire-sizing problem, namely, layer assignment for efficient timing closure. Assigning all wires to thick metals improves timing; however, the routability of the design may be hurt. The challenge is to assign a minimal amount of wires to thick metals to meet timing constraints. In this brief, the minimum cost layer assignment problem is proven to be NP-complete. As a theoretical solution for NP-complete problems, a fully polynomial-time approximation scheme is proposed. The new algorithm can approximate the optimal layer assignment solution by a factor of 1 + isin in O(m log log M ldrn 3 isin2) time for 0 < isin < 1, where n is the number of nodes in the tree, m is the number of routing layers, and M is the maximum cost ratio among layers. This work presents the first theoretical advance for the timing-driven minimum cost layer assignment problem. In addition to its theoretical guarantee, the new algorithm is highly practical. Our experiments on 500 industrial test cases demonstrate that the new algorithm can run 2times faster than the optimal dynamic programming algorithm, with only 2% additional wire.

Investigation of actuating displacement performance of curved actuator by large-scalecomputation

In this paper, the electromechanical displacements of curved actuators such as THUNDERare calculated by the finite-element method to design the optimal configuration of curvedactuators. To predict the internal stress in the device due to the mismatch in coefficients ofthermal expansion, the adhesive as well as metal and PZT ceramic is also numericallymodeled by using hexahedral solid elements. Also, the nonlinear finite-element formulationis implemented to include the variation of material constants during the curing process andacquire more accurate actuating displacements. Because the modeling of these thinlayers causes the numbers of degree of freedom to increase, large-scale structuralanalyses are performed in a cluster system in this study. The curved shape andinternal stress in the actuator are obtained by the cured curvature analysis, andthe displacement subject to the piezoelectric force by an applied voltage is alsocalculated to investigate the performance of curved actuators. The thickness of metalsand adhesive, and the number of metal layers, are chosen as design variables.

Rapid Method to Account for Process Variation in Full-Chip Capacitance Extraction

Full-chip capacitance extraction programs based on lookup techniques, such as HILEX/CUP , can be enhanced to rigorously account for process variations in the dimensions of very large scale integration interconnect wires with only modest additional computational effort. HILEX/CUP extracts interconnect capacitance from layout using analytical models with reasonable accuracy. These extracted capacitances are strictly valid only for the nominal interconnect dimensions; the networked nature of capacitive relationships in dense, complex interconnect structures precludes simple extrapolations of capacitance with dimensional changes. However, the derivatives, with respect to linewidth variation of the analytical models, can be accumulated along with the capacitance itself for each interacting pair of nodes. A numerically computed derivative with respect to metal and dielectric layer thickness variation can also be accumulated. Each node pair's extracted capacitance and its gradient with respect to linewidth and thickness variation on each metal and dielectric layer can be stored in a file. Thus, instead of storing a scalar value for each extracted capacitance, a vector of 3I+1 values will be stored for capacitance and its gradient, where I is the number of metal layers. Subsequently, this gradient information can be used during circuit simulation in conjunction with any arbitrary vector of interconnect process variations to perform sensitivity analysis of circuit performance.

Analysis of flip-chip packaging challenges on copper/low-k interconnects

An interfacial-fracture-mechanics-based simulation methodology has been developed to study the flip-chip packaging effect on the copper/low-k structures. Multilevel submodeling techniques have been used to bridge the scale difference between the flip-chip packages and the metal/dielectric stacks. To achieve a smaller feature size and higher speed in future chips, SiO/sub 2/ can be replaced with low-k dielectric material in all via and trench layers or the number of metal layers can be increased. The effect of both packaging options has been evaluated. With either option, the future flip-chip copper/low-k packages are facing higher possibilities of adhesive or cohesive failure near the low-k interface. This paper provides a quantitative evaluation of the increased risk, thus providing guidelines to the next level of low-k flip-chip packages.

Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI)

A multilevel interconnect architecture design methodology that optimizes the interconnect cross-sectional dimensions of each metal layer is introduced that reduces logic macrocell area, cycle time, power consumption or number of metal layers. The predictive capability of this methodology, which is based on a stochastic wiring distribution, provides insight into defining the process technology parameters for current and future generations of microprocessors and application-specific integrated circuits (ASICs). Using this methodology on an ASIC logic macrocell case study for the 100 nm technology generation, the optimized n-tier multilevel interconnect architecture reduces macrocell area by 32%, cycle time by 16% or number of wiring tracks required on the topmost tier by 62% compared to a conventional design where pitches are doubled for every successive pair of levels. A new repeater insertion methodology is also described that further enhances gigascale integration (GSI) system performance. By using repeaters, a further reduction of 70% in macrocell area, 18% in cycle time, 25% in number of metal levels or 44% in power dissipation is achieved, when compared to an n-tier design without repeaters. The key distinguishing feature of the methodology is its comprehensive framework that simultaneously solves two distinct problems-optimal wire sizing and wiring layer assignment-using independent constraints on maximum repeater area for efficient design space exploration to optimize the area, power, frequency, and metal levels of a GSI logic megacell.

ESD protection under grounded-up bond pads in 0.13 μm eight-level copper metal, fluorinated silicate glass low-k intermetal dielectric CMOS process technology

Electrostatic discharge (ESD) protection device under the grounded-up bond pad is investigated in 0.13 /spl mu/m full eight-level copper metal CMOS process technology with fluorinated silicate glass (FSG) low-k intermetal dielectric (IMD), The bonding force and power produces no cracking and no noticeable change in the second breakdown trigger point (V/sub t2/) I/sub t2/). High current I-V measured from the different level metal layer stack structures shows that 1) I/sub t2/ depends very weakly on metal layers used, as expected due to certain junction power dissipation criterion and 2) V/sub t2/ increases with the number of metal layers, The origin of the latter is increased dynamic impedance for increased metal layer number, as clarified by a simple RC model. The model also yields the intrinsic second breakdown trigger current and voltage for the underlying ESD protection device, Successfully configuring ESD protection circuits under the bond pads, therefore, not only is wholly free from the traditional area consumption, but also can substantially relax design constraints, enabling much more flexible and robust ESD schemes for various applications,.

The challenge of signal integrity in deep-submicrometer CMOS technology

Advances in interconnect technologies, such as the increase in the number of metal layers, stacked vias, and the reduced routing pitch, have played a key role to continuously improve integrated circuit design and operating speed. However several parasitic effects jeopardize the benefits of scale-down. Understanding and predicting interconnect behavior is vital for designing high-performance integrated circuit design. Our paper first reviews the interconnect parasitic effects and examines their impact on circuit behavior and their increase due to lithography reduction, with special emphasis on propagation delay, lateral coupling, and crosstalk-induced delay. The problem of signal integrity characterization is then discussed. In our review of the different well-established measurement methodologies such as direct probing, S-parameters, e-beam sampling and on-chip sampling, we point out weaknesses, frequency ranges, drawbacks, and overall performances of these techniques. Subsequently, the on-chip sampling system is described. This features a precise line-domain characterization of the voltage waveform directly within the interconnect and shows its application in the accurate evaluation of propagation delay, crosstalk, and crosstalk-induced delay along interconnects in deep-submicrometer technology. The sensor parts are described in detail, together with signal integrity patterns and their implementation in 0.18-/spl mu/m CMOS technology. Measurements obtained with this technique are presented. In the third part, we discuss the simulation issues, describe the two- and three-dimensional interconnect modeling problems, and review the active device models applicable to deep-submicrometer technologies in order to agree on measurements and simulations. These studies result in a set of guidelines concerning the choice of interconnect models. The last part outlines the design rules to be used by designers and their implementation within computer-aided design (CAD) tools to achieve signal integrity compliance. From a 0.18-/spl mu/m technology are derived critical variables such as crosstalk tolerance margin, maximum coupling length, and the criteria for adding a signal repeater. From these, values for low-dielectric and copper interconnects have been selected.

Interconnect scaling scenario using a chip level interconnect model

This paper describes an interconnect scaling scenario, which considers the impact of metal aspect ratio and pitch at each layer, new interconnect materials, and improved circuit design techniques. A new design methodology for a multilevel interconnect scheme is proposed on the basis of a chip level interconnect model. The design rule, the number of metal layers, and selection of interconnect materials at each device generation are projected using this methodology. It is shown that the 0.13-/spl mu/m CMOS generation requires not only new interconnect materials but also improved circuit design techniques such as variable pitch router and insertion of repeater buffers. A high-performance LSI in the 0.13-/spl mu/m CMOS generation needs seven layers using Cu interconnect and low-k dielectrics.