Interconnect scaling scenario using a chip level interconnect model

Abstract

This paper describes an interconnect scaling scenario, which considers the impact of metal aspect ratio and pitch at each layer, new interconnect materials, and improved circuit design techniques. A new design methodology for a multilevel interconnect scheme is proposed on the basis of a chip level interconnect model. The design rule, the number of metal layers, and selection of interconnect materials at each device generation are projected using this methodology. It is shown that the 0.13-/spl mu/m CMOS generation requires not only new interconnect materials but also improved circuit design techniques such as variable pitch router and insertion of repeater buffers. A high-performance LSI in the 0.13-/spl mu/m CMOS generation needs seven layers using Cu interconnect and low-k dielectrics.