Number Of Logic Elements Research Articles

Notification Oriented Paradigm to Digital Hardware — A benchmark evaluation with Random Forest algorithm

The Notification Oriented Paradigm (NOP) emerges as an alternative to develop and execute applications. The NOP brings a new inference concept based on precise notifying collaborative minimal entities. This inference implicitly allows achieving decoupled solutions, thereby enabling parallelism at a granularity level as fine-grained as possible in the envisaged computational platform. Previous research has proposed a digital circuit solution based on the NOP model, which is called NOP to Digital Hardware (DH), as a sort of High-Level Synthesis (HLS) prototype tool. The results with NOP-DH were encouraging indeed. However, the previous NOP-DH works lack benchmarks that exploit well-known algorithms against known HLS tools, such as the Vivado HLS tool, which is one of the suitable commercial HLS solutions. This work proposes evaluating the NOP-DH applied to develop the well-known Random Forest algorithm. The Random Forest is a popular Machine Learning algorithm used in several classification and regression applications. Due to the high number of logic-causal evaluations in the Random Forest algorithm and the possibility of running them in parallel, it is suitable for envisaged benchmark purpose. Experiments were performed to compare NOP-DH, and two Vivado HLS approaches (an ad hoc code and a hls4ml tool-based code) in terms of performance, amount of logic elements, maximum frequency, and the number of predictions per second. Those experiments demonstrated that NOP-DH circuits achieve better results concerning the number of logical elements and prediction rates, with some scalability limitations as a drawback. On average, the NOP-DH uses 52.5% fewer resources, and the number of predictions per second is 4.7 times higher than Vivado HLS. Finally, our codes are made publicly available at https://nop.dainf.ct.utfpr.edu.br/nop-public/nop-dh-random-forest-algorithm.

РЕАЛИЗАЦИЯ В БАЗИСЕ ПЛИС РЕЛЯТОРНЫХ КОНТРОЛИРУЮЩИХ ОПРОСНЫХ УСТРОЙСТВ ЦИФРОВЫХ СИГНАЛОВ

The requirements for modern means of technical control and functional diagnostics ofequipment for critical applications are formulated, one of which is the processing of diagnosticinformation at a real-time pace. It is noted that for working with digital diagnostic signals, relational monitoring polling devices based on the apparatus of ordinal logic, which gives a significanttime gain over traditional binary logic, are promising. The hardware implementation of ordinal-logical polling devices in the FPGA basis, along with the obvious advantages of the developmentstage, will allow for operational reconfiguration of the internal structure to adapt to thechanging operating conditions of the control object. The hardware implementation of two knowndevices is considered. A variable priority device is used to identify the sensor that has detected afailure or malfunction, with the possibility of setting the sensor number from which the survey willbegin, and the direction of traversing the sensor tuple. The device of centralized control of a groupof objects is used to search for an extreme (maximum or minimum) digital diagnostic signal withsimultaneous determination of the number of the corresponding sensor in one clock cycle of themonitoring and diagnostic system. The development of combinational data schemes of monitoringsurvey devices was carried out by means of ISE Design Suite 14.7. The positive results of testingthe algorithms of the created models are presented, summarized in tables of the states of the inputsand outputs of the circuits and illustrated by time diagrams of binary signals at the terminals ofthe circuits. An estimate of the required FPGA resource costs is given, expressed in the number oflogical elements and user contacts. Also, using the example of low integration devices and themost resource-intensive samples, the upper and lower estimates of the number of FPGAs of varioustypes of the Xilinx Spartan-6, Xilinx Virtex-4 families and the domestic 5576/5578 series ofJSC KTC Electronics are given. It is established that with the number of diagnostic sensors up to200, depending on the FPGA family, up to 17 low integration chips and up to 7 resource-intensivechips are required to implement one monitoring polling device.

Реализация оптимального построения комбинационного устройства и оценка надёжности по выходному напряжению

The theoretical propositions of the algebra of logic are considered. It is noted that the current microcircuitry based on the algebra of logic contains logical statements: true (yes) is a logical unit, false (no) is a logical zero. Based on the given logical function: ((ABC)×D + A×(BCD) + A×(BC)×D + (AB)×(CD), frontal, minimal, transformed minimal variants of the combination device are implemented, as well as minimized variants in the bases "AND-NOT" and "OR-NOT". A combination device based on import-substituting chips of 155, 176 series has been designed. The analysis of the obtained devices is made from the standpoint of technical and economic indicators, in particular, an assessment of the number of logic elements used, an assessment of the symmetry of the structure, as a result, a reduction in energy consumption, an increase in performance, improvements in parameters for reliability of functioning, a decrease in weight and size characteristics. Assuming that the law of change of the information parameter U1 is close to linear, taking into account the effect of temperature as boundary values for the elements of the applied microcircuits, taking the values -60 °C and +120°. Accordingly, the parametric reliability of the optimal implementation of the device according to the output voltage parameter is calculated. The conclusion is made about the inverse dependence of parametric reliability on temperature growth. A recommendation is given when evaluating parametric reliability for a number of other information parameters about the need to take into account both the number of chips used and the type of their interconnections.

A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application

Nowadays, a huge amount of digital data is frequently changed among different embedded devices over wireless communication technologies. Data security is considered an important parameter for avoiding information loss and preventing cyber-crimes. This research article details the low power high-speed hardware architectures for the efficient field programmable gate array (FPGA) implementation of the advanced encryption standard (AES) algorithm to provide data security. This work does not depend on the Look-Up Table (LUTs) for the implementation the SubBytes and InvSubBytes stages of transformations of the AES encryption and decryption; this new architecture uses combinational logical circuits for implementing SubBytes and InvSubBytes transformation. Due to the elimination of LUTs, unwanted delays are eliminated in this architecture and a subpipelining structure is introduced for improving the speed of the AES algorithm. Here, modified positive polarity reed muller (MPPRM) architecture is inserted to reduce the total hardware requirements, and comparisons are made with different implementations. With MPPRM architecture introduced in SubBytes stages, an efficient mixcolumn and invmixcolumn architecture that is suited to subpipelined round units is added. The performances of the proposed AES-MPPRM architecture is analyzed in terms of number of slice registers, flip flops, number of slice LUTs, number of logical elements, slices, bonded IOB, operating frequency and delay. There are five different AES architectures including LAES, AES-CTR, AES-CFA, AES-BSRD, and AES-EMCBE. The LUT of the AES-MPPRM architecture designed in the Spartan 6 is reduced up to 15.45% when compared to the AES-BSRD.

Design of Digital Operational Units with Low Power Consumption

The lowering of power consumption in CMOS VLSI digital systems is one of the most important problems that appear now for developers of CAD systems. One of the effective approaches to lowering the dynamic power consumption is creation of an algorithmic description of the VHDL project, which provides for the deactivation of some functional blocks which are not necessary in particular moments. Contemporary synthesizers fulfill the high level synthesis of logic circuits by substitution of description of each VHDL construction with functionally structural description of a proper logic subcircuit. The results of digital logic circuit synthesis (the number of logic elements and power consumption) depend significantly on initial VHDL code. During initial VHDL code development it is possible to use different approaches to improve some parameters of synthesized logic circuit. At the algorithmic level of the digital design, it is necessary to provide for disconnection of the units, which cause the higher power consumption. In this paper such methods of algorithmic VHDL description of logic circuit are studied. The efficiency of the proposed methods is compared with the traditional method of VHDL-description which does not take the aspect of power con­sumption into account and is oriented only to the correct functionality of the developed logic circuit. To estimate the power consumption of logic circuits the approach is used which allows applying high-speed logical VHDL-simulation of structural descriptions (netlists) of logic circuits instead of slow SPICE simulation. The main conclusion of the provided study is the following: the clock gating and the storage of operand values for complex operations as well as zero value setting for simple ones are effective methods for the VHDL description of operational units with low power consumption implemented in the CMOS basis.

Повышение быстродействия многоразрядного арифметико-логического устройства

In modern microprocessors to reduce the time resources the arithmetic-logic units (ALU) with an increased organization of arithmetic carry, characterized by high speed, compared to ALU with sequential organization of the arithmetic carry, are commonly used. However, while increasing the bit number of the input operands, the operating time of ALU of ALU with the accelerated arithmetic carry increases linearly depending on the number of bits. Therefore, the development of ALU, providing higher performance than the existing known solutions, is an actual task. In this work the analysis of ALU with sequential and accelerated organization of the arithmetic carry has been performed. To increase the speed of the operation, a multi-bit ALU has been developed. The simulation of ALU circuits has been executed in Altera Quartus –II CAD environment. The comparison has been performed by the number of logical elements and the maximum delay as a result of modeling the ALU circuits for 4, 8, 16, 32, and 64 bits. A scheme for checking the results has been implemented to confirm the reliability of developed ALU. As a result, it has been found that when performing operations with the 64-bit operands, the developed ALU reduces the maximum delay by 53 % compared to ALU with sequential arithmetic carry and by 35.5 % compared to ALU with the accelerated arithmetic carry, respectively.

Data processing by end devices in IoT systems

Internet of things (IoT) systems are making a significant contribution to the growth of global traffic. There is a tendency towards a decrease in the volume of transmitted and stored data, for which various approaches are used. Most of these approaches involve traditional cloud and gateway processing, leaving the endpoints idle in the process. The article discusses the correlation method of data processing on the end device. The results of the study of the maximum performance when implemented on FPGAs with different orders of the matched filter N and different bit widths of the input data stream are presented. A huge number of devices have been connected to the network for a long time. On the Internet of Things, communication must occur between things (without human intervention). This paper presents a correlation method for processing data on end devices and reducing the amount of data transmitted over the network. Instead of expensive and complex network devices, developers can use cheap and proven low-speed Internet of Things (ZigBee, NB IoT, BLE) solutions for data transfer. The novelty lies in one of the features of this approach: the use of components for analysis, rather than a complete copy of the signals, as well as processing directly on the sensor. The advantage of this approach allows you to reduce the number of operations and complexity of implementation, in contrast to other methods focused on the cloud computing paradigm. We provide results for correlation values and the number of logical elements (LE) when implemented on the FPGA, depending on the number of elements in the correlator. This allows to maintain a balance between the required calculation accuracy and spent hardware resources, as well as to simplify the end device.

A Fast AES Hardware Security Module for Internet of Things Applications

As the Internet of Things is used in various fields, Internet of Things security has become important. Since most Internet of Things devices is implemented as embedded systems, they provide a software-implemented encryption algorithm. Most embedded systems use relatively low-performance CPUs and the software processes data serially, making it difficult to process complex security algorithms in real-time. Therefore, it is necessary to have a stable encryption module with less impact on system performance. In this paper, we designed an AES hardware security module. Because it is implemented with dedicated hardware, it can process a strong encryption algorithm in real time without affecting the performance of the system. The proposed AES hardware module is designed using Verilog-HDL, tested in ModelSim and implemented in Altera FPGA Cycloneâ…£. The designed AES hardware adopts parallel processing technique and pipeline structure considering the computational complexity and processing order of the algorithm. As a result, it is faster than AES modules implemented in software. In addition, its latency was reduced to about 280 ns, which is about 16 % of the latency of the previous AES hardware module. Not only did the performance improve, but the number of logic elements and registers also decreased to 83.6% and 92.8%, respectively. The proposed AES hardware module is verified by applying it to a door lock system and is expected to be applied to various Internet of Things devices.

Improving Characteristics of LUT-Based Moore FSMs

Almost any digital system includes sequential blocks which can be represented using a model of finite state machine (FSM). It is very important to improve such characteristics of FSM circuits as the number of logic elements, operating frequency and consumed energy. The paper proposes a novel design method targeting a decrease in the number of look-up table (LUT) elements in logic circuits of FPGA-based Moore FSMs. The method is based on using two sets of variables for encoding the collections of outputs. It results in a partition of the set of outputs by two blocks. The outputs from the first block depend on state variables, the outputs from the second block on additional variables. A method is proposed for splitting the set of outputs. The conditions for using the proposed method are given. An example of synthesis is shown. The results of experiments with standard benchmarks are discussed. The experiments outcomes show that the proposed approach allows diminishing the number of LUTs and consumed energy. Also, it leads to an increase in the operating frequency. The method targets rather complex FSMs when the number of state variables exceeds the number of LUT’s inputs.

Novel Binary Signed-Digit Addition Algorithm for FPGA Implementation

Signed-digit (SD) number representation systems have been studied for high-speed arithmetic. One important property of the SD number system is the possibility of performing addition without long carry chain. However, many numbers of logic elements are required when the number representation system and such an adder are realized on a logic circuit. In this study, we propose a new adder on the binary SD number system. The proposed adder uses more circuit area than the conventional SD adders when those adders are realized on ASIC. However, the proposed adder uses 20% less number of logic elements than the conventional SD adder when those adders are realized on a field-programmable gate array (FPGA) which is made up of 4-input 1-output LUT such as Intel Cyclone IV FPGA.

FPGA implementation of fast digital FIR and IIR filters

SummaryThe demand for digital signal processing optimized solutions grows drastically in the modern years, especially in the field of communication and modern signal processing circuits. The finite impulse response (FIR) and an infinite impulse response (IIR) filters play a crucial role in the design of any complex signal processing system. This paper exemplifies the conventional moving average (MA) FIR filters, fast MA FIR filters using look‐ahead arithmetic, the conventional IIR filters using combination of integrator and comb sections (CIC) method, and the fast IIR filters using look‐ahead arithmetic in detail. Altera EP4CE115F29C7 field‐programmable gate array (FPGA) device using Quartus II 13.1 synthesis tool has been used to implement these filters. The performance metrics like the number of Logic Elements (LEs), the performance, and the power immoderation simulation results are compared with the normal and fast MA FIR and IIR filters, respectively. The first‐order IIR conventional filter has 153.4 MHz performance shown in simulation result, the same filter with look‐ahead level 1 has 189.79 MHz performance, and the fast filter with level 2 has 199.96 MHz performance. In addition, with the MA FIR filters, an 8‐tap MA FIR filter using CIC method has 166.09 MHz performance, the same filter using look‐ahead with level 1 has 167.22 MHz performance, and the same filter using look‐ahead with level 2 has 168.56 MHz performance. The proposed FIR and IIR filter is designed efficiently in terms of speed for the application of VLSI signal processing environment.

High speed and low area decision feed-back equalizer with novel memory less distributed arithmetic filter

In this paper an efficient implementation of decision feed back equalizer (DFE) is carried out using novel memory less distributed arithmetic (NMLDA) filter. In wireless transmission systems, DFEs are used to mitigate the inter-symbol interference (ISI). The ISI is occurred due to multi-path propagation of the transmitted signal. High data rate systems demand higher order filters in DFE architectures which increase complexity in hardware design. In our proposed NMLDA design, we have used multiplexers and enhanced compressor adders in place of memory unit and conventional adders. The proposed design occupies lower area and gives higher throughput, when compared to MAC based filter and all other memory based DA filter architectures. By using proposed NMLDA based DFE, the ISI errors in transmission signal, will be minimized and the performance of the transmission system will be enhanced. We have synthesized the NMLDA of 32-tap, 16-tap, 8-tap and 4-tap filters and implemented them on FPGA device. The proposed design has nearly 70% less number of logical elements than OBC DA and 50% less than MDA and offers better throughput than the existing designs when implemented on Altera Cyclone III EP3C55F484C6.

Radix-8 Design Alternatives of Fast Two Operands Interleaved Multiplication with Enhanced Architecture

Abstract In this paper, we proposed different comparable reconfigurable hardware implementations for the radix-8 fast two operands multiplier coprocessor using Karatsuba method and Booth recording method by employing carry save (CSA) and kogge stone adders (KSA) on Wallace tree organization. The proposed designs utilized ALTERA Cyclone IV FPGA family with target chip device EP4CGX–22CF19C7 along with simulation package. Also, the proposed designs were synthesized and benchmarked in terms of the maximum operational frequency, the total path delay, the total design area and the total thermal power dissipation. The experimental results revealed that the best multiplication architecture was belonging to Wallace Tree CSA based Radix-8 Booth multiplier (WCBM) which recorded: critical path delay of 14.103 ns, maximum operational frequency of 90.83 MHz, hardware design area (number of logic elements) of 14249 LEs, and total thermal power dissipation estimated as 217.56 mW. Consequently, WCBM method can be efficiently employed to enhance the speed of computation for many multiplication based applications such embedded system designs for public key cryptography.

Cost effective FPGA Implementation of Right-to-Left Modular Exponentiation with NAF-Representation

Modular exponentiation is an exponentiation performed over a modulus. It is useful in computer science, especially in the field of public-key cryptography. Most technological applications of modular arithmetic involve exponentials with very large numbers. In this paper, we propose a high radix reconfigurable implementation for the Right-to-Left Modular Exponentiation with NAF-Representation by exploiting the maximum possible parallelism of the internal operations. The proposed design targeted the ALTERA Cyclone IV FPGA (EP4CGX22CF19C7) along with Quartus II simulation package. The proposed design was evaluated in terms of the maximum operational frequency, the total path delay, the total design area and the total thermal power dissipation. The synthesized results revealed that the proposed high radix architecture implementation has recorded: critical path delay of 25.5 ns, maximum operational frequency of 44.59 MHz, hardware design area (number of logic elements) of 2556 LEs, and total thermal power dissipation estimated as 221.82 mW. Consequently, the proposed modular exponentiation architecture can be efficiently employed by many public key cryptographic mechanisms.

Performance Analysis of 128-bit Modular Inverse Based Extended Euclidean Using Altera FPGA Kit

Modular inverse is a division operation performed over a modulus and is considered as a fundamental operation for many public-key cryptosystems. Extended Euclidean Algorithm (EEA) is considered one of the most efficient algorithms to compute the modular multiplicative inverse of two coprime numbers. In this paper, we are reporting on the FPGA implementation of 128-bit modular inverse unit using Extended Euclidean Algorithm (EEA) algorithm with maximum possible parallelism of the internal operations. To verify the deposed implementation, we have synthesized our VHDL coding using ALTERA Cyclone IV FPGA with target device EP4CGX22CF19C7 using Quartus II simulation package. The experimental results showed that the proposed implementation recorded a critical path delay of 16.84 ns with maximum operational frequency of 72.7 MHz. Also, the area of the proposed design was estimated as the number of logic elements (LEs) utilized by the proposed unit which is reported as 7157 LEs. Finally, the power dissipation of the proposed using was estimated as the total FPGA thermal power dissipation and reported as 231.41 mW. Hence, the proposed modular inverse module can be efficiently embedded with many FPGA based cryptographic applications.

Low power binomial coefficient architecture for unused spectrum detector

Recently, low power architecture is the major requirement in wireless devices. Cognitive radio is the most significant technology to realize the problem of choosing the temporarily unused channels (Sarijari et al. in EURASIP J Wireless Commun Netw 2015:221, 2015). In this paper, the binomial coefficient (nCk) architecture is proposed for finding the possibilities of detecting the unused spectrum in the cognitive radio network. A novel factorial algorithm is designed using a modified parallel multiplier with Vedic multiplication method (Maharaja in Vedic mathematics, Motilal Banarsidass Publishers Pvt Ltd, Delhi, 2001). Compared to existing factorial algorithm (Saha et al. in Microelectron J 42:1343–1352, 2011), the proposed novel factorial algorithm can perform low power, high speed and occupy less number of logic elements because of the simple data-path reduction method using decoder circuit. A new binomial coefficient architecture is designed using the proposed factorial algorithm. The proposed modules are designed and implemented in Altera Cyclone II FPGA family.

Implementation and Evaluation of FPGA-based Annealing Processor for Ising Model by use of Resource Sharing

The non-von Neumann computer architecture has been widely studied to prepare us for the post-Moore era. The authors implemented this kind of architecture, which finds the lower energy state of the Ising model using circuit operations inspired by simulated annealing in SRAM-based integrated circuits. Our previous prototype was suited for the Ising model because of its simple and typical structure such as its three-dimensional lattice topology, but it could not be used in real world applications. A reconfigurable prototyping environment is needed to develop the architecture and to make it suitable for applications. Here, we describe an FPGA-based prototyping environment to develop the annealing processor's architecture for the Ising model. We implemented the new architecture using a prototyping environment. The new architecture performs approximated simulated annealing for the Ising model, and it supports a highly complex topology. It consists of units having fully-connected multiple spins. Multiple units are placed in a two-dimensional lattice topology, and neighboring units are connected to perform interactions between spins. The number of logic elements was reduced by sharing the operator among multiple spins within the unit. Furthermore, a pseudo-random number generator, which produces random pulse sequences for annealing, is also shared among all the units. As a result, the number of logic elements was reduced to less than 1/10, and the solution accuracy became comparable to that of a conventional computer's simulated annealing.

High Performance Design of Elgamal Cyrptographic Algorithm using Vedic Mathematics

Objectives: Vedic mathematics contains 16 formulae or Sutras. Employing these shortcut formulae in the computations of Elgamal cryptographic algorithm will reduce the logic elements, layout area and power consumption. Methods/Statistical Analysis: Simulation programming for the paper has been done through Verilog HDL code in MODELSIM software and performance parameters like speed, power etc., using XILINX software. Findings: In this paper, when employing these Vedic formulae, lesser number of logic elements are consumed when compared with conventional method. Improvements/ Applications: By investigating the various Sutras in Vedic mathematics, it has been observed that speed is increased and layout area is minimized.

VLSI –Fuzzy Decision Controller Based ECG Encoder

The electrocardiogram (ECG) is an important biomedical signal and widely used to monitor the function of heart. Continuous remote monitoring of ECG signal of the patients has become necessary nowadays. Since ECG sensors produces large amount of data continuously, it is difficult to store and transmit ECG records. Hence VLSI based data compression techniques are used for low power wireless transmission and transmit more data with limited bandwidth. In this perspective, a novel VLSI (Very Large Scale Integration) based data compression algorithm using fuzzy based decision controller is proposed in which four second order prediction equations had been mathematically formulated based on the present and past 2 samples. In order to select the appropriate equation based on the present, difference of the past samples and slope directions of sample, a fuzzy based decision controller is implemented for encoding. The difference between predicted and original data is encoded and listed in the lookup table. The lookup table maintains a variable length code at every instant to represents a shorter code length for frequently occurring difference values and longer code length for less probable difference values. The proposed method shows an improvement of 2.667 compression ratio, delay, time period and power consumption than the existing system with compromise in the number of logical elements.

PERSPECTIVE PROGRAMMABLE LOGIC INTEGRATED CIRCUITS FPGA FROM ALTERA

Purpose Comparison of characteristics of advanced programmable logic microchips Altera's Stratix 10 and Arria 10 and FPGAs of the previous generation Stratix V and Arria V Methods of Research The article deals with the analysis of new programmable logic microchips FPGA (Altera Company), one of the world’s famous FPGA manufacturers, designed and announced in 2013. The ways of FPGA development, requirements, specifications and capacities of Stratix 10 and Arria 10 as compaired with that of the previous generation are given here. The main specific feature of the Stratix 10 is the 10 nm technology in manufacturing of transistors Intel 3D Tri-Gate; and the 20 nm technology for Arria 10, encreasing the number of logic elements and, as a consequence, its efficiency while decreasing power consumption. Results The results of the research may be interested to specialists in the field of designing and usage of digital devices based on FPGA.