Normal Adder Research Articles

Low power low area VLSI implementation of adaptive FIR filter using DA for decision feed back equalizer

In this paper, a low-complexity pipelined adaptive FIR filter is designed using Distributed Arithmetic (DA) architecture for signal processing applications. Generally adaptive filters will occupy more area and power consumption because of using memories in the filters for partial product (PP) generation. To get rid of this, We use the pipeline concept to reduce the registers in the filters and also to reduce the area further compressor adders are used in the adaptive filter architectures instead of using normal adders. With these two concepts the area and power consumption of the adaptive filters will be reduced. The proposed design is coded in Verilog HDL language and synthesized in Synapsis design compiler tool with SAED 90 nm technology for finding the area, power, minimum sampling period, maximum sampling frequency, area delay product (ADP), power delay product (PDP). By using proposed adaptive filter we can design and implement higher order filters more easily and also the complexity of the proposed design is very less when compared with the existing designs. When we observe the synthesis results the proposed design will occupy 30% less area when compared with the two memories based existing architecture. Also the power consumption is 25% less when compared with the block based adaptive filters. The ADP and PDP of the proposed design is very less when compared with existing architectures. The proposed design is well suited for signal processing application designs such as adaptive decision feed back equalizers for removing the signal noises and inter symbol interference, hearing aids, ECG signal analysis and software defined radio.

Concurrent fault detection and location with minimal overhead in Ling parallel prefix adders with a scheme for fault tolerant Ling prefix adders

In this paper a scheme for concurrent error detection (CED) in Ling parallel prefix adders is put forth leveraging the even-odd independence inherent in this class of adders. The proposed technique is based on the simplest form of fault detection i.e. duplicating and comparing results. This is achieved utilizing the unique even-odd independence feature in the Ling prefix structure. This feature is exploited to implement the fault tolerant Ling prefix adder with minimum overhead.The area and power overhead for CED are examined and results show that they reduce as the word size increases with the area overhead going down to less than 10% and power overhead to about 13% for a 64-bit adder. Delay is extraneous as the normal adder operation is not affected due to CED. The proposed fault tolerant adder design is compared with earlier schemes and results show that the proposed design gives an improvement of about 30% in area, 10% in PDP and about 40% in the ADP. Cadence Incisive Unified Simulator v6.1 is used for the functional simulation. Detailed analysis of the performance has been carried out at TSMC 180 nm process node (slow-normal library) using Cadence RTL compiler v7.1. Hardware synthesis has been performed to compute the metrics area, power and delay.

Modular Adders Based on Reversible Circuits

Reversible logic is a computing model which has gained remarkable heed in recent years due to its properties that lead to ultra power and reliable circuits. Reversible circuits are key, for quantum computing. In this work we propose the usage of modular adders, in particular modular 2n-1 adders, with the use of reversible logic. Analysis comparison with normal adders and modular adders with reversible gates.

Design of New Reconfigurable Architecture for Implementing a Least Mean Square Finite Impulse Response Filter Using Borrow Select Subtraction (BSLS)

A design of reconfigurable architecture of FIR filter has been implemented using a Least Mean Square (LMS) adaptive filter. LMS adaptive filter is mainly sued for reducing the coefficients of the filter. Generally, a LMS filter contains normal adder, subtractor, mixer and a delay part. Most of the concepts deal with an adder namely Full Adder (FA), Ripple Carry Adder (RCA), Carry Select Adder (CSLA), etc., Instead of using CSLA; Borrow Select Subtractor (BSLS) is used in LMS filter architecture. By using BSLA LMS adaptive filter in a reconfigurable FIR filter architecture in the proposed scheme, the area, power and delay will be reduced. The proposed scheme achieves better performance when compared to an existing scheme. The proposed method is implemented in ModelSim tool and efficiency has been calculated by using the device Virtex 6 Low Power in Xilinx ISE Design Suite 12.4.

Halving the cost of quantum addition

We improve the number of T gates needed to perform an n-bit adder from 8n+O(1) to 4n+O(1). We do so via a "temporary logical-AND" construction which uses four T gates to store the logical-AND of two qubits into an ancilla and zero T gates to later erase the ancilla. This construction is equivalent to one by Jones, except that our framing makes it clear that the technique is far more widely applicable than previously realized. Temporary logical-ANDs can be applied to integer arithmetic, modular arithmetic, rotation synthesis, the quantum Fourier transform, Shor's algorithm, Grover oracles, and many other circuits. Because T gates dominate the cost of quantum computation based on the surface code, and temporary logical-ANDs are widely applicable, this represents a significant reduction in projected costs of quantum computation. In addition to our n-bit adder, we present an n-bit controlled adder circuit with T-count of 8n+O(1), a temporary adder that can be computed for the same cost as the normal adder but whose result can be kept until it is later uncomputed without using T gates, and discuss some other constructions whose T-count is improved by the temporary logical-AND.

Survey: Performance Analysis of FIR Filter Design Using Modified Truncation Multiplier with SQRT based Carry Select Adder

A recent years of technology development in Signal processing application a FIR (Finite impulse response) filter design will have a highly compactable with high performance and low power in all digital signal processing application, such as audio processing, signal processing, software define radio and so on. Now a days in our environment will have more signal noises, and fluctuation due to technology development, here the Filter design is mainly configuring the priority to reduce the signal noises and fluctuation in all type of gadgets. In this project, the design contains Transpose form of high performance and high speed filter design using finite impulse response (FIR) filter with technique of pipelined inherently and supported multiple constant multiplication (MCM) in significant with saving power computation. In digital signal processing, the multiplier is a highly required thing, the example of parallel multiplier provide a high-speed and highly reliable method for multiplication, but this parallel multiplier will take large area and also power consumption. In the FIR filter design, multiplier and adders is the maximum priority will take to give the performance, but this MCM multiplier and Adders tree architecture will take large area and maximum power consumption in signal processing. So our Proposed approach of this work, will have replace the MCM multiplier to Truncated Multiplier and using the technique of Truncated based both Signed and Unsigned Operation with SQRT based Carry Select Adder (CSLA), and also replace the normal adders in FIR Filter to SQRT based Carry Select Adder (CSLA). In the proposed system of FIR Filter design results to be analysis with signed and unsigned Truncation using modified technique of HSCG-SCS based SQRT-CSLA and hence proved its more efficient than existing design, such as FIR filter for Truncation multiplier with SQRT-CSLA based Adders, FIR filter for Truncation multiplier with BEC based Adders, FIR filter for Truncation multiplier with RCA, and FIR filter for Truncation multiplier with Common Boolean logic based RCA, and finally implemented this design on VHDL with help of Xilinx FPGA-S6LX9 and shown the performance of proposed design in terms of delay, area, and power.

A Low Cost Image De-noising Implementation Using Low Area CSLA for Impulse Noise Removal

In the process of image acquisition and transmission, data can be corrupted by impulse noise. This paper presented the removal of impulse noise in medical image by using Very Large Scale Integrated circuit (VLSI) implementation. The Low Cost Reduced Simple Edge Preserved De-noising (LCRSEPD) technique is introduced using Low Area Carry Select Adder (CSLA) to remove the salt and pepper noise instead of normal adder. Thus, LCRSEPD technique preserves visual performance and edge features in terms of quality and quantitative evaluation. By optimizing the architecture, low cost RSEPD can achieve low computational complexity that will reflect in area, power and delay. Compared to the previous VLSI implementations, the LCRSEPD implementation with CSLA adder has achieved good medical image quality and less hardware cost due to the reduction of area, power and delay.