Low power low area VLSI implementation of adaptive FIR filter using DA for decision feed back equalizer

Abstract

In this paper, a low-complexity pipelined adaptive FIR filter is designed using Distributed Arithmetic (DA) architecture for signal processing applications. Generally adaptive filters will occupy more area and power consumption because of using memories in the filters for partial product (PP) generation. To get rid of this, We use the pipeline concept to reduce the registers in the filters and also to reduce the area further compressor adders are used in the adaptive filter architectures instead of using normal adders. With these two concepts the area and power consumption of the adaptive filters will be reduced. The proposed design is coded in Verilog HDL language and synthesized in Synapsis design compiler tool with SAED 90 nm technology for finding the area, power, minimum sampling period, maximum sampling frequency, area delay product (ADP), power delay product (PDP). By using proposed adaptive filter we can design and implement higher order filters more easily and also the complexity of the proposed design is very less when compared with the existing designs. When we observe the synthesis results the proposed design will occupy 30% less area when compared with the two memories based existing architecture. Also the power consumption is 25% less when compared with the block based adaptive filters. The ADP and PDP of the proposed design is very less when compared with existing architectures. The proposed design is well suited for signal processing application designs such as adaptive decision feed back equalizers for removing the signal noises and inter symbol interference, hearing aids, ECG signal analysis and software defined radio.