Abstract
We improve the number of T gates needed to perform an n-bit adder from 8n+O(1) to 4n+O(1). We do so via a "temporary logical-AND" construction which uses four T gates to store the logical-AND of two qubits into an ancilla and zero T gates to later erase the ancilla. This construction is equivalent to one by Jones, except that our framing makes it clear that the technique is far more widely applicable than previously realized. Temporary logical-ANDs can be applied to integer arithmetic, modular arithmetic, rotation synthesis, the quantum Fourier transform, Shor's algorithm, Grover oracles, and many other circuits. Because T gates dominate the cost of quantum computation based on the surface code, and temporary logical-ANDs are widely applicable, this represents a significant reduction in projected costs of quantum computation. In addition to our n-bit adder, we present an n-bit controlled adder circuit with T-count of 8n+O(1), a temporary adder that can be computed for the same cost as the normal adder but whose result can be kept until it is later uncomputed without using T gates, and discuss some other constructions whose T-count is improved by the temporary logical-AND.
Highlights
The surface code [5, 8, 21, 22, 11] is a quantum error correcting code that works on a 2D nearest-neighbour array of qubits and achieves a threshold error rate of approximately 1%
This makes the surface code a likely component in the architecture of future error corrected quantum computers, because 2D arrays of qubits with nearest-neighbor connections are possible with many qubit technologies [23, 4, 12, 18, 17] and other well understood error correcting codes either have lower thresholds or require stronger connectivity
It is interesting to consider if addition or temporary logical-ANDs can be done with still fewer T gates
Summary
The surface code [5, 8, 21, 22, 11] is a quantum error correcting code that works on a 2D nearest-neighbour array of qubits and achieves a threshold error rate of approximately 1%. We thereby halve the number of T gates needed to perform Toffoli gates that appear in compute/uncompute pairs and halve the T-count of Cuccaro-style adders from 8n + O(1) to 4n + O(1).
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