Non-volatile Memory Technologies Research Articles

Research on Improved Crystallization Properties and Underlying Mechanism of the Sb2Te3 Phase-Change Thin Film by Inserting Sn15Sb85 Layers.

As a non-volatile semiconductor memory technology, phase-change memory has a wide range of application prospects as a result of the excellent comprehensive performance. In this paper, multilayer thin films based on Sb2Te3 material were designed and prepared by inserting the Sn15Sb85 layer. The thermal and electrical properties of superlattice-like Sb2Te3/Sn15Sb85 phase-change films can be adjusted by controlling the thickness ratio of Sb2Te3/Sn15Sb85. In comparison to the monolayer Sb2Te3 film, the multilayer layer Sb2Te3/Sn15Sb85 materials have a higher crystallization temperature, larger crystallization activation energy, and longer data lifetime, indicating the great improvement of thermal stability. The changes in the phase structure and vibrational modes of multilayer Sb2Te3/Sn15Sb85 films were characterized by X-ray diffraction and Raman spectroscopy, respectively. The presence of Sn15Sb85 layers restrains grain growth and refines the grain size. The multilayer Sb2Te3/Sn15Sb85 films exhibit better surface flatness, smaller surface potential undulation, and lower thickness variations than single-layer Sb2Te3. Phase-change memory cells based on the [Sb2Te3 (1 nm)/Sn15Sb85 (9 nm)]5 thin film has a lower threshold voltage (1.9 V) and threshold current (3.1 μA) compared to the Ge2Sb2Te5 film. Meanwhile, the electrical heating model of a phase-change memory cell based on a [Sb2Te3 (1 nm)/Sn15Sb85 (9 nm)]5 multilayer structure was established by multiphysics coupling analysis, proving the great improvement in heat transfer performance and efficiency. The experimental and theoretical studies confirm that the insertion of the Sn15Sb85 layer can significantly improve the crystallization properties of Sb2Te3 films, paving the way for optimizing the phase-change materials by regulating the microstructural parameters.

A quantum sensing metrology for magnetic memories

Magnetic random access memory (MRAM) is a leading emergent memory technology that is poised to replace current non-volatile memory technologies such as eFlash. However, controlling and improving distributions of device properties becomes a key enabler of new applications at this stage of technology development. Here, we introduce a non-contact metrology technique deploying scanning NV magnetometry (SNVM) to investigate MRAM performance at the individual bit level. We demonstrate magnetic reversal characterization in individual, <60 nm-sized bits, to extract key magnetic properties, thermal stability, and switching statistics, and thereby gauge bit-to-bit uniformity. We showcase the performance of our method by benchmarking two distinct bit etching processes immediately after pattern formation. In contrast to ensemble averaging methods such as perpendicular magneto-optical Kerr effect, we show that it is possible to identify out of distribution (tail-bits) bits that seem associated to the edges of the array, enabling failure analysis of tail bits. Our findings highlight the potential of nanoscale quantum sensing of MRAM devices for early-stage screening in the processing line, paving the way for future incorporation of this nanoscale characterization tool in the semiconductor industry.

Ferro-Electric RAM

Ferroelectric RAM (FRAM) is a promising non-volatile memory technology that combines the advantages of both DRAM and Flash memory. FRAM offers fast read and write speeds, low power consumption, and high endurance, making it suitable for a wide range of applications. It stores data by utilizing the ferroelectric properties of certain materials, which can retain their polarization even when the power is off. This allows FRAM to offer high-speed operation with low power consumption, making it ideal for use in IoT devices, smart cards, and automotive systems

Enhancing Lifetime and Performance of MLC NVM Caches Using Embedded Trace Buffers

Large volumes of on-chip and off-chip memory are required by contemporary applications. Emerging non-volatile memory technologies including STT-RAM, PCM, and ReRAM are becoming popular for on-chip and off-chip memories as a result of their desirable properties. Compared to traditional memory technologies such as SRAM and DRAM, they have minimal leakage current and high packing density. Non Volatile Memories (NVM), however, have a low write endurance, a high write latency, and high write energy. Non-volatile Single Level Cell (SLC) memories can store a single bit of data in each memory cell, whereas Multi Level Cells (MLC) can store two or more bits in each memory cell. Although MLC NVMs have substantially higher packing density than SLCs, their lifetime and access speed are key concerns. For a given cache size, MLC caches consume 1.84× less space and 2.62× less leakage power than SLC caches. We propose Trace buffer Assisted Non-volatile Memory Cache (TANC), an approach that increases the lifespan and performance of MLC-based last-level caches using the underutilized Embedded Trace Buffers (ETB). TANC improves the lifetime of MLC LLCs up to 4.36× and decreases average memory access time by 4% compared to SLC NVM LLCs and by 6.41× and 11%, respectively, compared to baseline MLC LLCs.

Stable and repeatable ZrO2 RRAM achieved by NiO barrier layer for negative set phenomenon elimination

Resistive random-access memory (RRAM) is a promising non-volatile memory technology due to its fast operation, low power consumption, and high reliability. However, the negative set phenomenon remains a challenge for RRAM, which can lead to the deterioration of device switching parameters. In this study, we successfully addressed this issue by inserting a NiO blocking layer between the ZrO2 and Ag top electrodes in ZrO2-based RRAM. In addition, the resistive switching characteristics of the device are significantly enhanced by the incorporation of a p-type oxide NiO layer. Compared to single-layer ZrO2 devices, the double-layer Ag/NiO/ZrO2/ITO RRAM exhibits improved cycling durability (>500 cycles) and good retention time (3 × 104s). Our analysis of the device conduction mechanism and proposed resistive switching model suggest that oxygen vacancies play a connecting role in the reset process, leading to failed reset behavior. Through the incorporation of a p-type semiconductor NiO layer into ZrO2-based RRAMs, the interference of oxygen vacancies on the reset process can be effectively impeded. This approach not only provides an effective resolution to the unforeseen negative set phenomenon in RRAM devices, but it also holds paramount significance for the advancement of high-performance RRAMs.

Phase Change Heterostructure Memory with Oxygen-DopedSb2Te3 Layersfor Improved Durability and Reliability through Nano crystalline Island Formation.

Phase-change random access memory represents a notable advancement in nonvolatile memory technology; however, it faces challenges in terms of thermal stability and reliability, hindering its broader application. To mitigate these issues, doping and structural modification techniques such as phase-change heterostructures (PCH) are widely studied. Although doping typically enhances thermal stability, it can adversely affect the switching speed. Structural modifications such as PCH have struggled to sustain stable performance under high atmospheric conditions. In this study, these challenges are addressed by synergizing oxygen-doped Sb2Te3 (OST) with PCH technology. This study presents a novel approach in which OST significantly improves the crystallization temperature, power efficiency, and cyclability. Subsequently, the integration of the PCH technology bolsters the switching speed and further amplifies the device's reliability and endurance by refining the grain size (≈7nm). The resultant OST-PCH devices exhibit exceptional performance metrics, including a drift coefficient of 0.003 in the RESET state, endurance of ≈4 × 108 cycles, an switching speed of 300ns, and 67.6 pJ of RESET energy. These findings suggest that the OST-PCH devices show promise for integration into embedded systems, such as those found in automotive applications and Internet of Things devices.

Phase-change heterostructure with HfTe2 confinement sublayers for enhanced thermal efficiency and low-power operation through Joule heating localization

Although phase-change random-access memory (PCRAM) is a promising next-generation nonvolatile memory technology, challenges remain in terms of reducing energy consumption. This is primarily because the high thermal conductivities of phase-change materials (PCMs) promote Joule heating dissipation. Repeated phase transitions also induce long-range atomic diffusion, limiting the durability. To address these challenges, phase-change heterostructure (PCH) devices that incorporate confinement sublayers based on transition-metal dichalcogenide materials have been developed. In this study, we engineered a PCH device by integrating HfTe2, which has low thermal conductivity and excellent stability, into the PCM to realize PCRAM with enhanced thermal efficiency and structural stability. HEAT simulations were conducted to validate the superior heat confinement in the programming region of the HfTe2-based PCH device. Moreover, electrical measurements of the device demonstrated its outstanding performance, which was characterized by a low RESET current (∼1.6 mA), stable two-order ON/OFF ratio, and exceptional cycling endurance (∼2 × 107). The structural integrity of the HfTe2 confinement sublayer was confirmed using X-ray photoelectron spectroscopy and transmission electron microscopy. The material properties, including electrical conductivity, cohesive energy, and electronegativity, substantiated these findings. Collectively, these results revealed that the HfTe2-based PCH device can achieve significant improvements in performance and reliability compared with conventional PCRAM devices.

Modulating resistive switching in Ni0.5Zn0.5Fe2O4 memristors: The role of manganese doping concentrations

Memristors, recognized as key devices for mitigating the von Neumann bottleneck, show great potential in non-volatile memory technology. Their performance is fundamentally linked to the chemical composition and structural characteristics of their intermediate dielectric layer. Owing to the inherent advantages of metal oxides, such as their simplistic chemical makeup and superior thermal stability, memristors featuring a Metal-Insulator-Metal (MIM) sandwich structure with metal oxides as the intermediate layer have received extensive focus. In this study, a Pt/Ni0.5Zn0.5MnxFe2-xO4(NZMFO)/Pt composite film was prepared, and its resistance switching behavior was modulated by altering the doping concentration of Mnn+ in NZMFO. The experimental results indicate that altering the Mnn+ doping concentration does significantly impact the content of oxygen vacancies. As the concentration of Mnn+ increases from 0.10 to 0.20 at.%, the content of oxygen vacancies correspondingly rises from 46.58 % to 76.42 %. Concurrently, variations in Mnn+ doping concentration significantly alter the resistance switching properties of the Pt/NZMFO/Pt composite films. This includes elevating the set/reset voltage, diminishing the resistance ratio, and enhancing the durability with the augmentation of Mnn+ concentration. By meticulously adjusting the Mnn+ doping concentration, we can achieve a memristor characterized by superior performance across all metrics. Considering all performance aspects, this study determined that the Pt/NZMFO/Pt thin film memristor with x = 0.15 exhibits adequate endurance (100 cycles), high data retention, and stable set/reset voltage. This work underscores the critical role of Mnn+ doping concentration in optimizing the electrochemical properties of NZFO memristors, illustrating a strategic pathway to engineer memristive devices with enhanced performance for future non-volatile memory applications.

Multi-level storage in cleaved-gate ferroelectric FETs investigated by 3D phase-field-based quantum transport simulation

In this work, we investigate the feasibility of cleaved-gate ferroelectric FET (CG-FeFET) as multi-level cell (MLC) memory devices, by conducting 3-dimensional quantum transport simulations based on time-dependent-Ginzburg–Landau equation, and the non-equilibrium Green’s function method. Our results indicate that CG-FeFET can achieve multi-level operations by utilizing different thicknesses of the ferroelectric layer. We analyze the influence of electron–phonon interaction and also verify that CG-FeFET is robust to noise. Furthermore, we identify the critical role of the spacing between two ferroelectric layers in determining the memory window, considering the effects of polarization cancellation and electrostatic coupling. These findings provide valuable insights into designing stable and reliable nonvolatile memory technologies, which could offer potential solutions for high-density memory requirements.

2D Ferroic Materials for Nonvolatile Memory Applications.

The emerging nonvolatile memory technologies based on ferroic materials are promising for producing high-speed, low-power, and high-density memory in the field ofintegrated circuits. Long-range ferroic orders observed in 2D materials have triggered extensive research interest in 2D magnets, 2D ferroelectrics, 2D multiferroics, and their device applications. Devices based on 2D ferroic materials and heterostructures with an atomically smooth interface and ultrathin thickness have exhibited impressive properties and significant potential for developing advanced nonvolatile memory. In this context, a systematic review of emergent 2D ferroic materials is conducted here, emphasizing their recent research on nonvolatile memory applications, with a view to proposing brighter prospects for 2D magnetic materials, 2D ferroelectric materials, 2D multiferroic materials, and their relevant devices.

Intermittent-Aware Design Exploration of Systolic Array Using Various Non-Volatile Memory: A Comparative Study.

This paper conducts a comprehensive study on intermittent computing within IoT environments, emphasizing the interplay between different dataflows-row, weight, and output-and a variety of non-volatile memory technologies. We then delve into the architectural optimization of these systems using a spatial architecture, namely IDEA, with their processing elements efficiently arranged in a rhythmic pattern, providing enhanced performance in the presence of power failures. This exploration aims to highlight the diverse advantages and potential applications of each combination, offering a comparative perspective. In our findings, using IDEA for the row stationary dataflow with AlexNet on the CIFAR10 dataset, we observe a power efficiency gain of 2.7% and an average reduction of 21% in the required cycles. This study elucidates the potential of different architectural choices in enhancing energy efficiency and performance in IoT systems.

Insulator Metal Transition-Based Selector in Crossbar Memory Arrays

This article investigates resistive random access memory (ReRAM) crossbar memory arrays, which is a notable development in non-volatile memory technology. We highlight ReRAM’s competitive edge over NAND, NOR Flash, and phase-change memory (PCM), particularly in terms of endurance, speed, and energy efficiency. This paper focuses on the architecture of crossbar arrays, where memristive devices are positioned at intersecting metal wires. We emphasize the unique resistive switching mechanisms of memristors and the challenges of sneak path currents and delve into the roles and configurations of selectors, particularly focusing on the one-selector one-resistor (1S1R) architecture with an insulator–metal transition (IMT) based selector. We use SPICE simulations based on defined models to examine a 3 × 3 1S1R ReRAM array with vanadium dioxide selectors and titanium dioxide film memristors, assessing the impact of ambient temperature and critical IMT temperatures on array performance. We highlight the operational regions of low resistive state (LRS) and high resistive state (HRS), providing insights into the electrical behavior of these components under various conditions. Lastly, we demonstrate the impact of selector presence on sneak path currents. This research contributes to the overall understanding of ReRAM crossbar arrays integrated with IMT material-based selectors.

Kinetics of N- to M-Polar Switching in Ferroelectric Al1-xScxN Capacitors.

Ferroelectric wurtzite-type aluminum scandium nitride (Al1-xScxN) presents unique properties that can enhance the performance of non-volatile memory technologies. The realization of the full potential of Al1-xScxN requires a comprehensive understanding of the mechanism of polarization reversal and domain structure dynamics involved in the ferroelectric switching process. In this work, transient current integration measurements performed by a pulse switching method are combined with domain imaging by piezoresponse force microscopy (PFM) to investigate the kinetics of domain nucleation and wall motion during polarization reversal in Al0.85Sc0.15N capacitors. In the studied electric field range (from 4.4 to 5.6MVcm-1), ferroelectric switching proceeds via domain nucleation and wall movement. The currently available phenomenological models are shown to not fully capture all the details of the complex dynamics of polarization reversal in Al0.85Sc0.15N. PFM reveals a non-linear increase of both domain nucleation rate and lateral wall velocity during the switching process, as well as the dependency of the domain pattern on the polarization reversal direction. A continuously faster N- to M-polar switching upon cycling is reported and ascribed to an increasing number of M-polar nucleation sites and density of domain walls.

SPIMulator: A Spintronic Processing-In-Memory Simulator for Racetracks

In-memory processing is becoming a popular method to alleviate the memory bottleneck of the von Neumann computing model. With the goal of improving both latency and energy cost associated with such in-memory processing, emerging non-volatile memory technologies, such as Spintronic magnetic memory, are of particular interest as they can provide a near-SRAM read/write performance and eliminate nearly all static energy without experiencing any endurance limitations. Spintronic Racetrack Memory (RM) further addresses density concerns of spin-transfer torque memory (STT-MRAM). Moreover, it has recently been demonstrated that portions of RM nanowires can function as a polymorphic gate, which can be leveraged to implement multi-operand bulk bitwise operations. With more complex control, they can also be leveraged to build arithmetic integer and floating point processing in memory (PIM) primitives. This paper proposes SPIMulator, a Spintronic PIM sim ulator that can simulate the storage and PIM architecture of executing PIM commands in Racetrack memory. SPIMulator functionally models the polymorphic gate properties recently proposed for Racetrack memory, which allows transverse access that determines the number of ‘1’s in a segment of each Racetrack nanowire. From this simulation, SPIMulator can report real-time performance statistics such as cycle count and energy. Thus, SPIMulator simulates the multi-operand bit-wise logic operations recently proposed and can be easily extended to implement new PIM operations as they are developed. Due to the functional nature of SPIMulator, it can serve as a programming environment that allows development of PIM-based codes for verification of new acceleration algorithms. We demonstrate the value of SPIMulator through the modeling and estimations of performance and energy consumption of a variety of example applications, including the Advanced Encryption Standard (AES) for encryption primarily based on logical and look-up operations; multiplication of matrices, a frequent requirement in scientific, signal processing, and machine learning algorithms; and bitmap indices a common search table employed for database lookups.

A Scalable Wear Leveling Technique for Phase Change Memory

Phase Change Memory (PCM), one of the recently proposed non-volatile memory technologies, has been suffering from low write endurance. For example, a single-layer PCM cell could only be written approximately 10 8 . This limits the lifetime of a PCM-based memory to a few days rather than years when memory-intensive applications are running. Wear leveling techniques have been proposed to improve the write endurance of a PCM. Among those techniques, the region-based start-gap (RBSG) scheme is widely cited as achieving the highest lifetime. Based on our experiments, RBSG can achieve 97% of the ideal lifetime, but only for relatively small memory sizes (e.g., 8–32GB). As the memory size goes up, RBSG becomes less effective and its expected percentage of the ideal lifetime reduces to less than 57% for a 2TB PCM. In this article, we propose a table-based wear leveling scheme called block grouping to enhance the write endurance of a PCM with a negligible overhead. Our research results show that with a proper configuration and adoption of partial writes (writing back only 64B subblocks instead of a whole row to the PCM arrays) and internal row shift (shifting the subblocks in a row periodically so no subblock in a row will be written repeatedly), the proposed block grouping scheme could achieve 95% of the ideal lifetime on average for the Rodinia, NPB, and SPEC benchmarks with less than 1.74% performance overhead and up to 0.18% hardware overhead. Moreover, our scheme is scalable and achieves the same percentage of ideal lifetime for PCM of size from 8GB to 2TB. We also show that the proposed scheme can better tolerate memory write attacks than WoLFRaM (Wear Leveling and Fault Tolerance for Resistive Memories) and RBSG for a PCM of size 32GB or higher. Finally, we integrate an error-correcting pointer technique into our proposed block grouping scheme to make the PCM fault tolerant against hard errors.

Mathematically modeling of Ge-Sb-Te superlattice to estimate the physico-chemical characteristics

Superlattices are periodic arrangements of two or more different materials on a nanoscale. Ge-Sb-Te (Germanium-Antimony-Tellurium) superlattices are a type of material used in phase-change memory (PCM) technology. PCM is a non-volatile memory technology that relies on the reversible phase transition between amorphous and crystalline states in certain materials. This phase-change property, combined with the non-volatile nature of the material, makes it suitable for applications like phase-change memory in electronic devices. Topological and entropy indices are the mathematical tools that are helpful to estimate the physico-chemical characteristics of chemical compounds. In this article, we have calculated some reduced reverse degree-based topological indices and entropy indices for Ge-Sb-Te superlattice. Ravi et al. [32] examined the statistically significant relationship of reduced reverse degree-based topological indices with physico-chemical characteristics of drug structures and proposed regression models using entropy indices. In this context, our computed results can be helpful in predicting the physico-chemical characteristics of Ge-Sb-Te superlattices.

NVM-enhanced Machine Learning Inference in 6G Edge Computing

With the increasing popularization of smart terminals and real-time interactive applications, fast growing technical requirements push both academia and industry to look beyond 5G and conceptualize the sixth generation (6G) mobile network. Artificial intelligence (AI) with machine learning capacities at the edge is one crucial component of a 6G mobile network which makes various time-sensitive and high-stake services possible, e.g., smart security, virtual reality, self-driving vehicles. However, resource constraints, especially the memory limitation of edge servers, become major obstacles to deploying machine learning services at the edge. Fortunately, the new generation of non-volatile memory (NVM) provides new affordable memory resources that can be easily attached to existing edge servers. In this paper, we propose a novel machine learning application placement scheme using the NVM technology at the edge to reduce the end-to-end latency. Specifically, the proposed NVM-enhanced placement scheme takes into consideration the latency of various machine learning applications over NVM devices and the network. The corresponding optimization problem is exceedingly challenging, i.e., NP-hard. Therefore, we developed a novel approximation algorithm with both low computational complexity and theoretical guarantees. Experiments and extensive simulations using real-world applications highlight that our scheme provides significantly lower end-to-end latency compared with existing baselines.

Notice of Violation of IEEE Publication Principles: An Energy-Efficient Heterogeneous Memory Architecture for Future Dark Silicon Embedded Chip-Multiprocessors

Main memories play an important role in overall energy consumption of embedded systems. Using conventional memory technologies in future designs in nanoscale era causes a drastic increase in leakage power consumption and temperature-related problems. Emerging non-volatile memory (NVM) technologies offer many desirable characteristics such as near-zero leakage power, high density and non-volatility. They can significantly mitigate the issue of memory leakage power in future embedded chip-multiprocessor (eCMP) systems. However, they suffer from challenges such as limited write endurance and high write energy consumption which restrict them for adoption in modern memory systems. In this article, we present a convex optimization model to design a 3D stacked hybrid memory architecture in order to minimize the future embedded systems energy consumption in the dark silicon era. This proposed approach satisfies endurance constraint in order to design a reliable memory system. Our convex model optimizes numbers and placement of eDRAM and STT-RAM memory banks on the memory layer to exploit the advantages of both technologies in future eCMPs. Energy consumption, the main challenge in the dark silicon era, is represented as a major target in this work and it is minimized by the detailed optimization model in order to design a dark silicon aware 3D Chip-Multiprocessor. Experimental results show that in comparison with the Baseline memory design, the proposed architecture improves the energy consumption and performance of the 3D CMP on average about 61.33 and 9 percent respectively.

Coupling effects of interface charge trapping and polarization switching in HfO2-based ferroelectric field effect transistors

HfO2-based ferroelectric field-effect transistors (FeFETs) are regarded as one of the most promising non-volatile memory technologies in the future. However, the charge trapping phenomenon during the program/erase operation is still a challenge. In this work, we comprehensively investigate the behaviors of semiconductor/insulator interface charge trapping in HfO2-based FeFETs. Through analyzing the effects of the spatial distribution of interface traps and the polarization switching speed, the coupling effects of semiconductor/insulator interface charge trapping and polarization switching are recognized. We also find that the band tail state traps have much less influence on the electrical characteristics of the FeFETs than the deep level state traps. Through engineering the devices with band tail state traps with concentrations as small as possible, the influences of charge trapping could be effectively suppressed. Moreover, the gate voltage (VG) scanning rate has a significant influence on the interface charge trapping process due to the time dependent change of ferroelectric polarization. The largest memory window could be obtained by carefully choosing the VG scanning rate of the FeFETs based on the polarization switching speed. This work represents a key step for realizing highly reliable HfO2-based FeFETs.

A unified hybrid memory system for scalable deep learning and big data applications

Emerging non-volatile memory (NVM) technologies are of dynamic random access memory (DRAM)-like, high capacity, and low cost, at the expense of slower bandwidth and higher read/write latency compared to DRAM. Typically, NVM finds its primary application in serving as an extension of conventional DRAM to create hybrid memory systems tailored to non-uniform memory access (NUMA) architectures. This strategic integration offers the potential for high performance, enhanced capacity efficiency, and a favorable balance of cost considerations. Traditional NUMA memory management policies distribute data uniformly across both DRAM and NVM, overlooking the inherent performance gap between these heterogeneous memory systems. This challenge becomes particularly pronounced when provisioning resources for deep learning and big data applications in hybrid memory systems. To tackle the performance issues in the hybrid memory systems, we propose and develop a unified memory system, UniRedl, which automatically optimizes data migration between DRAM and NVM based on data access patterns and computation graphs of applications. To improve application performance, we provide a new memory allocation strategy named HiLowAlloc. We further design two data migration strategies in UniRedl, Idle Migration and Dynamic Migration, for management of hybrid memory systems. Specifically, Idle Migration aims to manage data placed in DRAM, while Dynamic Migration manages data saved in NVM. The experimental results demonstrate that on average UniRedl improves application performance by 33.2%, 20.6%, 19.0%, and 17.5% compared to the traditional NUMA, NUMA with anb, BMPM, and OIM, respectively. It also achieves 52.0%, 34.3%, 30.6%, 22.1% on average improvement in data locality against the state-of-the-art solutions.