Nonvolatile Memory Operation Research Articles

Unipolar polarization switching and high-endurance memory operation of HZO/Si anti-ferroelectric FETs

Abstract We experimentally demonstrate the anti-ferroelectric (AFE) behavior of a Hf1-xZrxO2 (HZO)/Si FET and its potential for high-endurance nonvolatile memory operation. The AFE-HZO FET with Zr content of 75 % exhibits a double polarization switching and half-loop switching of its double hysteresis under bipolar and unipolar bias conditions, respectively. The counterclockwise hysteresis in the transfer Id -Vg characteristics is demonstrated under unipolar Vg sweep through half-loop polarization in AFeFET. The steep subthreshold swing values were observed for both forward and backward Vg sweeps of Id -Vg curves for AFeFET under unipolar bias condition. The nonvolatile feature of AFeFET is achieved by introducing the optimized hold voltage of 1.3 V during the retention period. The threshold voltage shift can be realized by utilizing the unipolar program /erase Vg pulses. Also, the high-endurance properties of HZO/Si AFeFET are demonstrated under unipolar Vg stress with observable memory window up to 109 cycles without gate insulator breakdown.

Forming and compliance-free operation of low-energy, fast-switching HfOxSy/HfS2 memristors.

We demonstrate low energy, forming and compliance-free operation of a resistive memory obtained by the partial oxidation of a two-dimensional layered van-der-Waals semiconductor: hafnium disulfide (HfS2). Semiconductor-oxide heterostructures are achieved by low temperature (<300 °C) thermal oxidation of HfS2 under dry conditions, carefully controlling process parameters. The resulting HfOxSy/HfS2 heterostructures are integrated between metal contacts, forming vertical crossbar devices. Forming-free, compliance-free resistive switching between non-volatile states is demonstrated by applying voltage pulses and measuring the current response in time. We show non-volatile memory operation with an RON/ROFF of 102, programmable by 80 ns WRITE and ERASE operations. Multiple stable resistance states are achieved by modulating pulse width and amplitude, down to 60 ns, < 20 pJ operation. This demonstrates the capability of these devices for low-energy, fast-switching and multi-state programming. Resistance states were retained without fail at 150 °C over 104 s, showcasing the potential of these devices for long retention times and resilience to ageing. Low-energy resistive switching measurements were repeated under vacuum (8.6 mbar) showing unchanged characteristics and no dependence of the device on surrounding oxygen or water vapour. Using a technology computer-aided design (TCAD) tool, we explore the role of the semiconductor layer in tuning the device conductance and driving gradual resistive switching in 2D HfOx-based devices.

Shunt-free cryogenic memory using ferromagnetic insulator-based Josephson junctions

Magnetic Josephson junctions are the preferred candidate devices for designing fast and scalable cryogenic memory elements. This is especially the case for rapid single-flux quantum-based superconducting electronics, where the speed mismatch between logic and memory elements have remained a long-standing challenge. In this Letter, we demonstrate a simple tri-layer Josephson memory device using ferromagnetic insulating (FI) GdN-based S/FI/S vertical mesa-type junctions, with reliable nonvolatile memory operation without the need of a shunt resistor at 4.2 K. The characteristic frequency of our devices is approximately 90 GHz, corresponding to an IcRn product of 177 μV. We demonstrate a thorough study of the parameter spaces required for designing these devices and identify the scope for future improvements that can lead to further miniaturization and higher operating speed of these devices.

Nonvolatile memory operations using intersubband transitions in GaN/AlN resonant tunneling diodes grown on Si(111) substrates

Nonvolatile memory using intersubband transitions and quantum-well electron accumulation in GaN/AlN resonant tunneling diodes (RTDs) is a promising candidate for high-speed nonvolatile memory operating on a picosecond timescale. This memory has been fabricated on sapphire(0001) substrates to date because of the high affinity between the nitride materials and the substrate. However, the fabrication of this memory on Si(111) substrates is attractive to realize hybrid integration with Si devices and nonvolatile memory and three-dimensional integration such as chip-on-wafer and wafer-on-wafer. In this study, GaN/AlN RTDs are fabricated on a Si(111) substrate using metal-organic vapor phase epitaxy. The large strain caused by the differences in the thermal expansion coefficients and lattice constants between the Si(111) substrate and nitride materials are suppressed by a growth technique based on the insertion of low-temperature-grown AlGaN and thin AlN layers. The GaN/AlN RTDs fabricated on Si(111) substrates show clear GaN/AlN heterointerfaces and a high ON/OFF ratio of &amp;gt;220, which are equivalent to those for devices fabricated on sapphire(0001) substrates. However, the nonvolatile memory characteristics fluctuate by repeated write/erase memory operations. Evaluation of the ON/OFF switching time and endurance characteristics indicates that the instability of the nonvolatile memory characteristics is caused by electron leakage through deep levels in the quantum-well structure. Possible methods for suppressing this are discussed with an aim of realizing high-speed and high-endurance nonvolatile memory.

Nonvolatile Memory Organic Light-Emitting Transistors.

In the field of active-matrix organic light emitting display (AMOLED), large-size and ultra-high-definition AMOLED applications have escalated the demand for the integration density of driver chips. However, as Moore's Law approaches the limit, the traditional technology of improving integration density that relies on scaling down device dimension is facing a huge challenge. Thus, developing a multifunctional and highly integrated device is a promising route for improving the integration density of pixel circuits. Here, a novel nonvolatile memory ferroelectric organic light-emitting transistor (Fe-OLET) device which integrates the switching capability, light-emitting capability and nonvolatile memory function into a single device is reported. The nonvolatile memory function of Fe-OLET is achieved through the remnant polarization property of ferroelectric polymer, enabling the device to maintain light emission at zero gate bias. The reliable nonvolatile memory operations are also demonstrated. The proof-of-concept device optimized through interfacial modification approach exhibits 20 times improved field-effect mobility and five times increased luminance. The integration of nonvolatile memory, switching and light-emitting capabilities within Fe-OLET provides a promising internal-storage-driving paradigm, thus creating a new pathway for deploying storage capacitor-free circuitry to improve the pixel aperture ratio and the integration density of circuits toward the on-chip advanced display applications.

Highly Reliable and Secure PUF Using Resistive Memory Integrated Into a 28 nm CMOS Process

Owing to the increased demand for secure communication channels and authentication steps, physical unclonable functions (PUFs) are increasingly important for hardware security. In this article, we report a novel PUF architecture and generation scheme that utilizes the inherent program-time variation of resistive random access memory (ReRAM) cells as an entropy source. ReRAM cells are integrated into a standard 28 nm CMOS manufacturing process, and also show robust non-volatile memory operation. We generated a PUF data set larger than 10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\text{8}}$</tex-math> </inline-formula> bits and verified its randomness using a standard NIST test suite. Further verifications such as inter-and intra-hamming distance, 150 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> C data retention of PUF bits, and spatial co-relation tests confirm the high reliability of the generated PUF keys.

Enhancement of nonvolatile memory characteristics caused by GaN/AlN resonant tunneling diodes

This paper reports an enhancement of the nonvolatile memory characteristics of GaN/AlN resonant tunneling diodes (RTDs) by reducing the crystal defects in the quantum well structure. Pit-shaped crystal defects are strongly suppressed when pure N2, instead of a N2/H2 mixture, is used as a carrier gas and trimethylindium is introduced as a surfactant for metalorganic vapor phase epitaxy of the quantum well structure. In addition, the density of dislocations is lowered by controlling the growth conditions and structure of the buffer layer between a GaN/AlN RTD and a sapphire (0001) substrate. The leakage current through the quantum well structure is lowered, and an extremely high ON/OFF of >1300, which is 20 times higher than the values obtained in previous studies, is induced. Theoretical calculations based on Poisson’s equation and the Tsu–Esaki formula indicate that a high ON/OFF ratio of >103 can be enhanced by increasing the density of electrons accumulating in the quantum well to a level on the order of 1018 cm–3. Furthermore, nonvolatile memory operations were performed by inputting the sequential pulse voltages with a speed of nanosecond time scale which is faster than speeds of electron releases from the crystal defects. These results strongly indicate that the nonvolatile memory characteristics of GaN/AlN RTDs are due to intersubband transitions and electron accumulation in the quantum well and are not attributed to electron trapping by the crystal defects.

Interface Trap‐Free, 100% Yield, Wafer‐Scale, Non‐Volatile Optically‐Guided Memory Array from Cumulatively‐Stacked Small Molecules/Fluoropolymer/Copper‐Oxide Nanoparticles Heterostructure (Adv. Electron. Mater. 12/2022)

Optical Memories In article number 2200752, Hocheon Yoo and co-workers present a 4-inch wafer-scale 12 × 12 array of optically-guided memory transistors, which detects an alphabet G with non-volatile memory operation. In the proposed memory device, electron charge trapping occurs in copper-oxide nanoparticles under light illumination, allowing the device to act as a photodetection and memory storage operation.

Improvement in nonvolatile memory operations for metal–ferroelectric–insulator–semiconductor capacitors using HfZrO2 and ZrO2 thin films as ferroelectric and insulator layers

Metal–ferroelectric–insulator–semiconductor (MFIS) capacitors were characterized to elucidate the optimum design schemes for the ferroelectric field-effect transistor applications. The Hf1−x Zr x O2 (HZO) thin films (18 nm) were prepared on the SiO2 and ZrO2 insulator layers (ILs) with different film thicknesses. The choice of 10 nm thick ZrO2 IL was found to be an optimum condition to properly balance between the values of electric fields applied to the HZO (E HZO) and ZrO2 (E IL) layers, leading to effective improvement in capacitance coupling ratio and to suppression of charge injection for the MFIS capacitors. Furthermore, the crystalline natures of the crystallized HZO films were also found to be strategically controlled on the ZrO2 ILs, which can additionally enhance the E HZO with reducing the E IL. As consequences, the MFIS capacitors using 10 nm thick ZrO2 IL exhibited the ferroelectric memory window as large as 2.5 V at an application of ±5 V, which corresponds to 2.7 times wider value, compared to that obtained from the device using 2 nm thick SiO2 IL. Long-time memory retention and robust program endurance were also verified for the fabricated MFIS capacitors.

Photochromic Dithienylethene Monolayer-Modified Gold Nanoparticles as a Tunable Floating Gate in the Fabrication of Nonvolatile Organic Memory.

Nonvolatile memory (NVM) devices were fabricated by implanting a self-assembled monolayer (SAM) of functional dithienylethene (DTE) derivative on the gold nanoparticle (Au-NP) surface in a pentacene-based organic transistor. The Au-NPs and DTE served as a charge-trapping medium and tunneling barrier layer, respectively. The transfer characteristic of the NVM device showed a narrow hysteresis window and wide memory window, indicating that the DTE-SAM served as a variable barrier layer to regulate the trapping and detrapping of external free charges at the Au-NPs. The energy gap introduced by the DTE-SAM is modulated through photoisomerization between a ring-open form and a ring-closed form by absorbing UV or visible light. For a memory device, the ring-closed DTE allows more free charge injection into the trapping sites, and the ring-open one better retains the trapped charges. A longer anchoring alkanethiol chain at the DTE moiety can further extend the device's retention time. For the NVM operation, programming with the ring-closed DTE and then switching the DTE structure to the ring-open form for erasing can facilitate the charge trapping and charge retention with the same molecule compared to operating all in the ring-open form or all in the ring-closed form of DTE. The structural characterization and electronic characteristics of these devices are discussed in detail.

Actual origin and precise control of asymmetrical hysteresis in an individual CH3NH3PbI3 micro/nanowire for optical memory and logic operation.

Although CH3NH3PbI3 can present an excellent photoresponse to visible light, its application in solar cells and photodetectors is seriously hindered due to hysteresis behaviour. Moreover, for its origin, there exist different opinions. Herein, we demonstrate a route to realize precise control for the electrical transport of a single CH3NH3PbI3 micro/nanowire by constructing a two-terminal device with asymmetric Ag and C electrodes, and its hysteresis can be clearly identified as a synergistic effect of the redox reaction at the interface of the Ag electrode and the injection and ejection of holes in the interfacial traps of the C electrode rather than its bulk effect. The device can show superior bias amplitude and illumination intensity dependence of hysteresis loops with typical bipolar resistive switching features. Thus, an excellent multilevel nonvolatile optical memory can be effectively realized by the modulation of the illumination and bias, and moreover a logic OR gate operation can be successfully implemented with voltage and illumination as input signals as well. This work clearly reveals and provides a new insight of hysteresis origin that can be attributed to a synergistic effect of two asymmetrical electrode interfaces, and therefore precisely controlling its electrical transport to realize an outstanding application potential in multifunctional devices integrated with optical nonvolatile memory and logic OR gate operation.

Symmetric Reconfigurable Ferroelectric Transistor for Non-Volatile Memories to Diminish the Effects of Gate Leakage

Reconfigurable ferroelectric transistor (R-FEFET) is a variant of a ferroelectric transistor (FEFET), which utilizes two asymmetrically sized gate stacks to achieve voltage-controlled modulation in hysteresis and dynamic reconfigurability between volatile and non-volatile modes. However, due to a floating internal metal layer (IML), gate leakage (GL) can lead to a polarization-dependent shift in device characteristics over time. This degrades read disturb margins (RDM) and the non-volatile memory (NVM) robustness. In this work, we propose an R-FEFET with symmetric gate stacks to diminish the adverse effects of GL on NVM operation. Utilizing our new R-FEFET, we propose a two-transistor NVM (2T-R), which exhibits up to 12% higher energy efficiency, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\times $ </tex-math></inline-formula> increase in the RDM, and 14% lower area compared to an existing R-FEFET NVM. We also perform variation analysis showing a robust operation of the symmetric R-FEFET NVM.

High Speed and Large Memory Window Ferroelectric HfZrO₂ FinFET for High-Density Nonvolatile Memory

We fabricated the HfZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (HZO) ferroelectric fin field-effect transistors (Fe-FinFET) with fin width of 60 nm and gate length of 100 nm for ferroelectric nonvolatile memory operations. The fabricated Fe-FinFET exhibited a large memory window (MW) of 1.5 V and high (100 ns) program/erase speeds at ±5 V. After 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> program/erase cycles, the MW was maintained at 1.09 V and the retention time was measured up to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> s with no degradation. The fabricated HZO Fe-FinFET is compatible with the current FinFET process and has a high MW, a fast program/erase speed, and excellent reliability. Therefore, the fabricated Fe-FinFET is a promising candidate for high-density ferroelectric field-effect transistor memory applications.

Characterization of nanoscale vertical-channel charge-trap memory thin film transistors using oxide semiconducting active and trap layers

We fabricated vertical-channel charge-trap memory thin film transistors (V-CTM TFTs) using an In–Ga–Zn–O channel and ZnO charge trap layers, in which a solution-processed SiO2 spacer pattern was introduced to scale down the vertical-channel length below 190 nm. The vertical gate-stack structure was implemented by atomic-layer deposition with excellent film conformality. The V-CTM TFTs with channel lengths of 190 (S1) and 140 nm (S2) showed charge-trap-assisted wide memory windows of 12.0 and 10.1 V, respectively. The memory margins between the on- and off-programmed currents were estimated to be 1.2 × 105 and 5.1 × 102 with a program pulse duration of 100 ms for S1 and S2, respectively. The programmed states did not exhibit any degradation with a lapse of retention for 104 s. With reducing the channel length, the number of endurance cycles decreased from 5000 to 3000 cycles. A vertical integration of oxide-based CTM device scaled down to sub-150 nm could be verified to show sound nonvolatile memory operations, even though there remain some technical issues such as a higher level of off-current for S2.

A scheme for enabling the ultimate speed of threshold switching in phase change memory devices

Phase change materials exhibit threshold switching (TS) that establishes electrical conduction through amorphous material followed by Joule heating leading to its crystallization (set). However, achieving picosecond TS is one of the key challenges for realizing non-volatile memory operations closer to the speed of computing. Here, we present a trajectory map for enabling picosecond TS on the basis of exhaustive experimental results of voltage-dependent transient characteristics of Ge2Sb2Te5 phase-change memory (PCM) devices. We demonstrate strikingly faster switching, revealing an extraordinarily low delay time of less than 50 ps for an over-voltage equal to twice the threshold voltage. Moreover, a constant device current during the delay time validates the electronic nature of TS. This trajectory map will be useful for designing PCM device with SRAM-like speed.

Volatile and Nonvolatile Memory Operations Implemented in a Pt/HfO₂/Ti Memristor

Both nonvolatile and volatile characteristics are realized in the same Pt/HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Ti memristor by specific electrical operations. The resistance states of nonvolatile memory hardly change for over 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> s, whereas the low resistance state of volatile memory is unstable, and degenerates gradually into the high resistance state in hundreds of seconds. The volatile device was forming-free and realized only in clockwise voltage sweeping. Compared to the nonvolatile device, the operating current of volatile device was lower and showed obviously rectification characteristics. Emulations of synaptic plasticity including short-term plasticity, long-term plasticity, and spike-time-dependent-plasticity were achieved. Finally, the resistive switching mechanism of the volatile device was analyzed and assumed to be the trapping and detrapping of electrons by traps near the interface of Pt/HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> .

Design space exploration of hysteretic negative capacitance ferroelectric FETs based on static solutions of Landau–Khalatnikov model for nonvolatile memory applications

Systematic design space exploration of negative capacitance ferroelectric field-effect transistors (FeFETs) for nonvolatile memory operations was performed, combining load line analyses and circuit simulations. Unlike those FeFETs aiming at a steep subthreshold slope, the key design target here is to achieve bi-stable current versus voltage FET characteristics with appropriate hysteresis width (i.e. memory window). Remanent polarization, coercive voltage, and interfacial layer thickness were selected as design parameters. The results show that, if a ferroelectric gate dielectric film obeying ideal single-domain Landau–Khalatnikov model dynamics with reduced remanent polarization is available, ultralow voltage nonvolatile memories operating with sub-one volt voltage swing would become possible. An interesting feature of the negative capacitance FeFETs is that, unlike conventional multiple domain FeFETs, the memory window can be adjusted to a much smaller value than twice the coercive voltage. The lowered remanent polarization is required to suppress the depolarization field to an acceptable level for reliability. It is proposed that considering the abrupt polarization switching, three-transistor and two-transistor memory cells would be suitable for working and code storage memories, respectively.

Multilevel operation of GdOx-based resistive switching memory device fabricated by post-deposition annealing

Resistive switching memory has been studied actively for next-generation computing. Several binary oxides, such as HfO2 and Ta2O5, are widely adapted as resistive switching layers; however, there are several limitations to obtaining an energy- and area-efficient operation with sufficient reliability. Rare-earth oxide materials exhibit interesting resistive switching properties because of their reactivities with active anion species. In this study, atomic-layer-deposited GdOx films were investigated as an active switching layer for resistive switching memory. Post-deposition annealing of as-grown GdOx films enhanced the tunability of the resistance states, which can be useful for the multilevel operation of nonvolatile memory and neuromorphic computing applications. The effects of the crystallization and hygroscopic nature of the GdOx film are investigated for elucidating the change in the resistive switching characteristics and its underlying mechanism.

Growth and Characterization of GaN/AlN Resonant Tunneling Diodes for High‐Performance Nonvolatile Memory

GaN/AlN resonant tunneling diodes (RTDs) are studied to realize a high‐speed nonvolatile memory based on the intersubband transactions and electron accumulation in the quantum well, which has the potential to operate at picosecond time scales. The crystal quality of GaN/AlN RTDs is improved by changing the growth conditions and structure of the buffer layer. The surface roughness and dislocation density of the GaN/AlN RTDs are successfully suppressed, and clear ON/OFF switching due to intersubband transitions is observed by inputting pulse voltage sequences. However, the voltages for write and erase operations are changed by improving the crystal quality of GaN/AlN RTDs. The theoretical analysis of resonant levels in the GaN/AlN RTDs indicates that the voltages for write and erase operations are very sensitive to the well and barrier widths and the density of electrons accumulating in the quantum well. Based on the results, the design of GaN/AlN RTDs for higher‐performance nonvolatile memory operations is investigated.

Impact of oxide gate electrode for ferroelectric field-effect transistors with metal-ferroelectric-metal-insulator-semiconductor gate stack using undoped HfO2 thin films prepared by atomic layer deposition

Ferroelectric field-effect transistors (FETs) with a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) gate stack were fabricated and characterized to elucidate the key process parameters and to optimize the process conditions for guaranteeing nonvolatile memory operations of the device when the undoped HfO2 was employed as ferroelectric gate insulator. The impacts of top gate (TG) for the MFM part on the memory operations of the MFMIS-FETs were intensively investigated when the TG was chosen as metal Pt or oxide ITO electrode. The ferroelectric memory window of the MFMIS-FETs with ITO/HfO2/TiN/SiO2/Si gate stack increased to 3.8 V by properly modulating the areal ratio between two MFM and MIS capacitors. The memory margin as high as 104 was obtained during on- and off-program operations with a program pulse duration as short as 1 μs. There was not any marked degradation in the obtained memory margin even after a lapse of retention time of 104 s at 85 °C and repeated program cycles of 10,000. These obtained improvements in memory operations resulted from the fact that the choice of ITO TG could provide effective capping effects and passivate the interfaces.