Design space exploration of hysteretic negative capacitance ferroelectric FETs based on static solutions of Landau–Khalatnikov model for nonvolatile memory applications

Abstract

Systematic design space exploration of negative capacitance ferroelectric field-effect transistors (FeFETs) for nonvolatile memory operations was performed, combining load line analyses and circuit simulations. Unlike those FeFETs aiming at a steep subthreshold slope, the key design target here is to achieve bi-stable current versus voltage FET characteristics with appropriate hysteresis width (i.e. memory window). Remanent polarization, coercive voltage, and interfacial layer thickness were selected as design parameters. The results show that, if a ferroelectric gate dielectric film obeying ideal single-domain Landau–Khalatnikov model dynamics with reduced remanent polarization is available, ultralow voltage nonvolatile memories operating with sub-one volt voltage swing would become possible. An interesting feature of the negative capacitance FeFETs is that, unlike conventional multiple domain FeFETs, the memory window can be adjusted to a much smaller value than twice the coercive voltage. The lowered remanent polarization is required to suppress the depolarization field to an acceptable level for reliability. It is proposed that considering the abrupt polarization switching, three-transistor and two-transistor memory cells would be suitable for working and code storage memories, respectively.