Nonvolatile Memory Elements Research Articles

Charge Trap Transistor (CTT): An Embedded Fully Logic-Compatible Multiple-Time Programmable Non-Volatile Memory Element for High- $k$ -Metal-Gate CMOS Technologies

The availability of on-chip non-volatile memory for advanced high- $k$ -metal-gate CMOS technology nodes has been limited due to integration and scaling challenges as well as operational voltage incompatibilities, while its need continues to grow rapidly in modern high-performance systems. By exploiting intrinsic device self-heating enhanced charge trapping in as fabricated high- $k$ -metal-gate logic devices, we introduce a unique multiple-time programmable embedded non-volatile memory element, called the ‘charge trap transistor’ (CTT), for high- $k$ -metal-gate CMOS technologies. Functionality and feasibility of using CTT memory devices have been demonstrated on 22 nm planar and 14 nm FinFET technology platforms, including fully functional product prototype memory arrays. These transistor memory devices offer high density ( $\sim 0.144\mu\mathrm{m}^{2}$ /bit for 22 nm and $\sim 0.082\mu\mathrm{m}^{2}$ /bit for 14 nm technology), logic voltage compatible and low peak power operation (~4mW), and excellent retention for a fully integrated and scalable embedded non-volatile memory without added process complexity or masks.

Tunnel electroresistance in BiFeO3 junctions: size does matter

In ferroelectric tunnel junctions, the tunnel resistance depends on the polarization orientation of the ferroelectric tunnel barrier, giving rise to tunnel electroresistance. These devices are promising to be used as memristors in neuromorphic architectures and as non-volatile memory elements. For both applications, device scalability is essential, which requires a clear understanding of the relationship between polarization reversal and resistance change as the junction size shrinks. Here we show a robust tunnel electroresistance in BiFeO3-based junctions with diameters ranging from 1200 to 180 nm. We demonstrate that the tunnel electroresistance and the corresponding fraction of reversed ferroelectric domains change drastically with the junction diameter: while the micron-size junctions display a reversal in less than 10% of the area, the smallest junctions show an almost complete polarization reversal. Modeling the electric-field distribution, we highlight the critical role of the bottom electrode resistance which significantly diminishes the actual electric field applied to the ferroelectric barrier in the mixed polarization state. A polarization-dependent critical electric field below which further reversal is prohibited is found to explain the large differences between the ferroelectric switchability of nano- and micron-size junctions. Our results indicate that ferroelectric junctions are downscalable and suggest that specific junction shapes facilitate complete polarization reversal.

Flexible transparent memory cell: bipolar resistive switching via indium–tin oxide nanowire networks on a poly(dimethylsiloxane) substrate

This report describes the fabrication and resistive switching (RS) characteristics of a novel flexible transparent (FT) resistive random access memory (ReRAM) device with a Ag/indium–tin oxide (ITO) nanowire network/ITO capacitor deposited on a PDMS substrate. The transmittance of the device is ∼70% in the visible region, and it exhibits a stable high-resistance state (HRS) to low-resistance state (LRS) ratio (HRS/LRS ratio) in different bending states. The RS characteristics are attributed to the congregate state of oxygen vacancies at different voltages, and the difference between positive and negative bending is mainly contributed by the effect of stress on the conductive layer. The FT-ReRAM can be used as nonvolatile memory element in future flexible transparent devices.

Nonvolatile Random Access Memory and Energy Storage Based on Antiferroelectric Like Hysteresis in ZrO2

To date antiferroelectrics have not been considered as nonvolatile memory elements because a removal of the external field causes a depolarization, resulting in a loss of the stored information. In comparison to ferroelectrics, antiferroelectrics are known for their enhanced fatigue resistance. Therefore, the main scope of this study is the development of a new memory device concept that would enable the usage of antiferroelectrics as a nonvolatile material with improved wake‐up and enhanced endurance properties. Recent studies have shown antiferroelectric behavior in ZrO2, a material that is widely used in semiconductor industry, especially in dynamic random access memories. The basis of the new concept is the antiferroelectric hysteresis combined with the use of different workfunction electrodes that induce an internal bias field. Utilizing this approach, the field cycling endurance is drastically improved. Combining a comprehensive material study and electrical trap spectroscopy together with Landau–Ginzburg–Devonshire formalism, a proof of concept for a novel antiferroelectric random access memory is presented. For implementing a nonvolatile random access memory, the capacitors have to be realized in a 3D integrated version. These 3D integrated ZrO2 capacitors can be used as energy storage devices as well, showing record high energy storage density and very high energy efficiency values.

Circuit-Level Benchmarking of Access Devices for Resistive Nonvolatile Memory Arrays

Large-scale 3D crossbar arrays can enable both high-density Storage Class Memory (SCM) and novel non-Von Neumann computation. Such arrays require each nonvolatile memory (NVM) element to have its own non-linear Access Device (AD), to pass high currents through one or more selected cells yet maintain ultra-low leakage through all other cells. Typically, power consumption during write, not read margin, is the most stringent constraint for large $1{\rm AD}+1{\rm R}$ crossbar arrays. We extend our circuit-level SPICE simulations—previously performed just for large arrays of an AD based on Cu-containing Mixed-Ionic-Electronic-Conduction (MIEC)-materials together with a generic NVM element $(+1{\rm R})$ —to three additional diode-like ADs as well as three threshold-switching ADs. We show that the suitability of an AD for 1AD1R memories is strongly dependent upon both nonvolatile memory (NVM) and circuit parameters, as well as the AD's own intrinsic properties. We find that building large arrays $(\geq 1~{\rm Mb})$ with $\geq 10~\mu{\rm A}$ NVM current is only possible for MIEC ADs and moderate NVM switching voltage $(\leq 1.2~{\rm V})$ . None of the ADs studied here support larger NVM switching voltage $(\geq 1.2~{\rm V})$ unless switching current is $\leq 10~\mu{\rm A}$ . The effects of line resistance, low-current (10–100 pA) bias condition, stacking two ADs vertically, and reductions in TVS threshold current are all studied. The particular AD parameters that would need to be improved to affect each AD's prospects are discussed.

Logic Design Within Memristive Memories Using Memristor-Aided loGIC (MAGIC)

Realizing logic operations within passive crossbar memory arrays is a promising approach to enable novel computer architectures, different from conventional von Neumann architecture. Attractive candidates to enable such architectures are memristors, nonvolatile memory elements commonly used within a crossbar, that can also perform logic operations. In such novel architectures, data are stored and processed within the same entity, which we term as memristive memory processing unit (MPU). In this paper, Memristor-Aided loGIC (MAGIC) family is discussed with various design considerations and novel techniques to execute logic within an MPU. We present a novel resistive memory-the transpose memory, which adds additional functionality to the memristive memory, and compare it with a conventional memristive memory. A case study of an adder is presented to demonstrate the design issues discussed in this paper. We compare the proposed design techniques with the memristive IMPLY logic in terms of speed, area, and energy. Our evaluation shows that the proposed MAGIC design is 2.4 × faster and consumes 66.3% less energy as compared with the IMPLY-based computing for N-bit addition within memristive crossbar memory. Additionally, we compare the proposed design with IMPLY logic family on ISCAS-85 benchmarks, which shows significant improvements in speed (2×) and energy (10×), with similar area.

ChemInform Abstract: Multifunctional Magnetoelectric Materials for Device Applications

AbstractReview: 207 refs.

High mobility multibit nonvolatile memory elements based organic field effect transistors with large hysteresis

High mobility multibit nonvolatile memory elements based on organic field effect transistors with a thin layer of polyquinoline (PQ) were reported. The devices show a high mobility of 1.5 cm2 V−1 s−1 in the saturation region which is among the best reported for nonvolatile organic memory transistors. The multibit nonvolatile memory elements can be operated at voltage less than 100 V with good stability under continuous operation condition and show long retention time. The different initial scanning positive gate voltages to −100 V result in several ON states, while the scanning gate voltage from −100 V to positive voltage leads to same OFF state. The charge trapping model of electrons into the PQ layer was used to explain the origin of the memory properties.

Data retention in organic ferroelectric resistive switches

Solution-processed organic ferroelectric resistive switches could become the long-missing non-volatile memory elements in organic electronic devices. To this end, data retention in these devices should be characterized, understood and controlled. First, it is shown that the measurement protocol can strongly affect the ‘apparent’ retention time and a suitable protocol is identified. Second, it is shown by experimental and theoretical methods that partial depolarization of the ferroelectric is the major mechanism responsible for imperfect data retention. This depolarization occurs in close vicinity to the semiconductor-ferroelectric interface, is driven by energy minimization and is inherently present in this type of phase-separated polymer blends. Third, a direct relation between data retention and the charge injection barrier height of the resistive switch is demonstrated experimentally and numerically. Tuning the injection barrier height allows to improve retention by many orders of magnitude in time, albeit at the cost of a reduced on/off ratio.

An accurate locally active memristor model for S-type negative differential resistance in NbOx

A number of important commercial applications would benefit from the introduction of easily manufactured devices that exhibit current-controlled, or “S-type,” negative differential resistance (NDR). A leading example is emerging non-volatile memory based on crossbar array architectures. Due to the inherently linear current vs. voltage characteristics of candidate non-volatile memristor memory elements, individual memory cells in these crossbar arrays can be addressed only if a highly non-linear circuit element, termed a “selector,” is incorporated in the cell. Selectors based on a layer of niobium oxide sandwiched between two electrodes have been investigated by a number of groups because the NDR they exhibit provides a promisingly large non-linearity. We have developed a highly accurate compact dynamical model for their electrical conduction that shows that the NDR in these devices results from a thermal feedback mechanism. A series of electrothermal measurements and numerical simulations corroborate this model. These results reveal that the leakage currents can be minimized by thermally isolating the selector or by incorporating materials with larger activation energies for electron motion.

Versatile Phase Transfer Method for the Efficient Surface Functionalization of Gold Nanoparticles: Towards Controlled Nanoparticle Dispersion in a Polymer Matrix

In electronic devices based on hybrid materials such as nonvolatile memory elements (NVMEs), it is essential to control precisely the dispersion of metallic nanoparticles (NPs) in an insulating polymer matrix such as polystyrene in order to control the functionality of the device. In this work the incorporation of AuNPs in polystyrene films is controlled by tuning the surface functionalization of the metallic nanoparticles via ligand exchange. Two ligands with different structures were used for functionalization: 1-decanethiol and thiol-terminated polystyrene. This paper presents a versatile method for the modification of gold nanoparticles (AuNPs) with thiol-terminated polystyrene ligands via phase transfer process. An organic colloid of AuNPs (5±1 nm diameter) is obtained by the phase transfer process (from water to toluene) that allows exchanging the ligand adsorbed on AuNPs surface (hydrophilic citrate/tannic acid to hydrophobic thiols). The stability, size distribution, and precise location of modified AuNPs in the polymer matrix are obtained from UV-Vis spectroscopy, dynamic light scattering (DLS), and electron tomography. TEM tomographic 3D imaging demonstrates that the modification of AuNPs with thiol-terminated polystyrene results in homogeneous particle distribution in the polystyrene matrix compared to 1-decanethiol modified AuNPs for which a vertical phase separation with a homogeneous layer of AuNPs located at the bottom of the polymer matrix was observed.

Surface-type nonvolatile electric memory elements based on organic-on-organic CuPc-H2Pc heterojunction**Project supported by the GIK Institute of Engineering Science and Technology, Pakistan and Physical Technical Institute of Academy of Sciences of Tajikistan.

A novel surface-type nonvolatile electric memory elements based on organic semiconductors CuPc and H2Pc are fabricated by vacuum deposition of the CuPc and H2Pc films on preliminary deposited metallic (Ag and Cu) electrodes. The gap between Ag and Cu electrodes is 30–40 μm. For the current–voltage (I–V) characteristics the memory effect, switching effect, and negative differential resistance regions are observed. The switching mechanism is attributed to the electric-field-induced charge transfer. As a result the device switches from a low to a high-conductivity state and then back to a low conductivity state if the opposite polarity voltage is applied. The ratio of resistance at the high resistance state to that at the low resistance state is equal to 120–150. Under the switching condition, the electric current increases ∼ 80–100 times. A comparison between the forward and reverse I–V characteristics shows the presence of rectifying behavior.

Design of a hybrid non-volatile SRAM cell for concurrent SEU detection and correction

This paper presents a hybrid non-volatile (NV) SRAM cell with a new scheme for soft error tolerance. The proposed cell consists of a 6T SRAM core, a resistive RAM made of a transistor and a Programmable Metallization Cell. An additional transistor and a transmission gate are utilized for selecting a memory cell in the NVSRAM array. Concurrent error detection (CED) and correction capabilities are provided by connecting the NVSRAM array with a dual-rail checker; CED is accomplished using a dual-rail checker, while correction is accomplished by utilizing the restore operation, such that data from the non-volatile memory element is copied back to the SRAM core. The simulation results show that the proposed scheme is very efficient in terms of numerous figures of merit.

Exploring the Design Space for Crossbar Arrays Built With Mixed-Ionic-Electronic-Conduction (MIEC) Access Devices

Large-scale 3-D crossbar arrays offer a path to both high-density storage class memory and novel non-Von Neumann computation. However, such arrays require each non-volatile memory (NVM) element to have its own non-linear access device (AD), which must pass high currents through one or more selected cells yet maintain ultra-low leakage through all other cells. Using circuit-level SPICE simulations, we explore design constraints on crossbar arrays composed of a generic NVM element (+1R) together with the novel AD developed by our group, based on Cu-containing mixed-ionic-electronic-conduction (MIEC) materials. We show that power consumption during write, not read margin, is the most stringent constraint for large 1AD+1R crossbar arrays. As array size grows, in order to keep NVM write power-efficient, the voltage at which the AD “turns on” must outpace the NVM switching voltage. Failure to achieve this condition causes the total array power, injected into the array to ensure the success of the worst-case single-bit write, to greatly exceed the actual NVM write power. Extensive tolerancing results show that NVM switching current and other AD parameters (subthreshold slope and series resistance) are also important, but not to the same degree as AD and NVM voltage characteristics. We show that scaled MIEC devices (Voltage Margin V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ~ 1.54V) can support 1 Mb arrays for NVM switching voltages up to 1.2V, and that stacking two MIEC devices could enable ~2.4V. The impact of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> variability is quantified-we show that there is minimal degradation in write power and read margin at variabilities (standard deviation in V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ) not very different from those already demonstrated experimentally.

Air-stable, non-volatile resistive memory based on hybrid organic/inorganic nanocomposites

A non-volatile memory element based on organic/inorganic nanocomposites is presented. The device can be operated in ambient conditions, showing high retention time and long-term life time. The formation/rupture of metallic filaments in the organic matrix is investigated by HR-XPS and ToF-SIMS analysis, and is demonstrated to be the driving mechanism for the resistive switching.

Design of rewritable and read-only non-volatile optical memory elements using photochromic spiropyran-based salts as light-sensitive materials

Optical memory devices based on photoswitchable OFETs comprising light sensitive layers of photochromic spiropyran salts revealed advanced electrical characteristics and superior stability.

Impact of Total Ionizing Dose on the Data Retention of a 65 nm SONOS-Based NOR Flash

In this paper, the impact of total ionizing dose on the data retention behavior of a silicon-oxide-nitride-oxide-silicon-based NOR flash nonvolatile memory is studied for the first time on a deep sub-micron 65-nm complementary metal-oxide semiconductor technology node. The fundamental nonvolatile single-level cell memory element utilizes uniform Fowler-Nordheim (F-N) tunneling for both program and erase operations. The data retention behavior is investigated on a 4-Mb NOR Flash-based memory array at space-level total ionizing dose (TID) exposures up to 500 krad. Excessive TID exposure reduces the program-erase window but improves the thermal emission coefficient and, hence, improves data retention.

Simulation and comparison of two sequential logic-in-memory approaches using a dynamic electrochemical metallization cell model

Resistive switching devices are an emerging class of non-volatile memory elements suited for application in passive nano-crossbar arrays. These devices can be modeled as dynamical systems, i.e. memristive devices or memristors for short. The built-in non-linear switching kinetics of these devices enables the performance of ‘stateful’ logic operations and widens the applicability of memory arrays towards logic operations. In this work, two logic-in-memories approaches are studied by means of dynamical simulations. The first one is the initial ‘stateful’ logic concept introduced by Boghetti et al., and the second approach is the complementary switch-based concept later suggested by Linn et al. In both cases, the considered device is an electrochemical metallization cell for which good dynamical models are available. The study is limited to the comparison of elementary logic functions—multi-stage logic as well as parallelization features of both approaches are not considered here. A comparison of the elementary logic IMP and NAND operations in terms of reliability, switching energy and basic array compatibility is conducted, and crucial requirements for both approaches are identified.

Band alignment at memristive metal-oxide interfaces investigated by hard x-ray photoemission spectroscopy

Nonvolatile memory elements, known as memristors, have recently received an attention boost by introducing transition-metal oxide /transition-metal bilayer structures. These structures enable the engineering of the electrical properties of the devices and the removal of unwanted forming steps though a redox-reaction at the interface. This work provides much needed information for the understanding of memristive behavior in such devices by providing the first systematic study of the electronic band alignment at the interface, which plays essential role in charge carrier transport.

Influence of Heavy Ion Irradiation on Perpendicular-Anisotropy CoFeB-MgO Magnetic Tunnel Junctions

A non-volatile memory element called a perpendicular-anisotropy magnetic tunnel junction was fabricated using CoFeB/MgO/CoFeB film stack technology. It exhibits two stable resistance values, high or low, depending on the relative directions of the magnetizations of the two ferromagnetic CoFeB layers. After being programmed into the high resistance state with a current injection scheme based on the spin transfer torque theory, the tunnel junction was exposed to 15-MeV Si ions under different voltage stress conditions. The tested structure remained in the programmed high resistance state after being bombarded with 10-100 Si ions, even under the stressed situations. A time-domain analysis proved that this result is due to the perfect immunity of the tested magnetic tunnel junction to single event upsets. Some degradation in resistance due to the heavy-ion irradiation was detected through a precise parameter analysis based on a tunneling theory but it was negligibly small (1%). There were no statistically significant changes in the thermal stability factor before and after irradiation, and this means the long-term retention properties remained unchanged.