A new segmented architecture is presented to improve the dynamic and static performance of the current steering digital-to-analog converters (DACs). In the proposed architecture instead of a single binary DAC, distributed binary cells are used. So the effect of the mismatch and timing errors of the binary cells are not accumulated and are averaged out. For realization of the MSB unit cells those binary cells are reused to form the larger weighted unit cells. Realization of the MSB unit cells with smaller cells results in improved dynamic performances as the effects of gradient errors are minimized and the effects of nonlinear parasitic capacitances are reduced. The DAC has been designed in 180 nm five-metal nwell CMOS process. The simulation results show that the DAC can achieve a maximum spurious free dynamic range (SFDR) of 70.99 dB at 2.93 MHz signal for a sampling rate of 1 GSPS considering the mismatch effects. For 1 GSPS sampling rate the simulated Nyquist SFDR is >70 dB with mismatch. The simulated third order intermodulation distortion (IM3) of the DAC with mismatch effect is 71.40 dB, for a dual tone test with 491.21 and 495.12 MHz signals. The DAC is optimized for digital signal synthesis applications in wireless base stations and other communication applications. The power dissipation of the DAC is 78.21 mW at 498.05 MHz signal for a sampling rate of 1 GSPS with 1.8 V supply.