Nonlinear CMOS Research Articles

Phase-matched third-harmonic generation in silicon nitride waveguides.

Third-harmonic generation (THG) in silicon nitride waveguides is an ideal source of coherent visible light, suited for ultrafast pulse characterization, telecom signal monitoring and self-referenced comb generation due to its relatively large nonlinear susceptibility and CMOS compatibility. We demonstrate third-harmonic generation in silicon nitride waveguides where a fundamental transverse mode at 1,596 nm is phase-matched to a TM02 mode at 532 nm, confirmed by the far-field image. We experimentally measure the waveguide width-dependent phase-matched wavelength with a peak-power-normalized conversion efficiency of 5.78 × 10-7 %/W2 over a 660-μm-long interaction length.

Nonlinear demosaicking method and apparatus for nonlinear CMOS image sensors exhibiting low-density salt-and-pepper noise

Simple demosaicking methods designed for linear CMOS image sensors, such as MATLAB’s demosaic function, may be used with a monotonic nonlinear sensor having a Bayer color filter array (CFA). However, such methods may be inadequate at handling dynamic salt-and-pepper noise (SPN), i.e., outlier pixels, which is expected in images taken with a nonlinear sensor. Although SPN is present with linear sensors, nonlinear sensors express low-density light-dependent SPN that requires filtering. Extending a recent work on dynamic SPN filtering of a nonlinear sensor, we propose, evaluate, and verify a nonlinear method and apparatus to demosaic images, taken with a Bayer CFA, while simultaneously filtering the SPN. The approach relies on the use of weighted medians to filter the SPN, especially at densities that imply isolated outliers in small neighborhoods, while determining an accurate red, green, and blue (RGB) color at every pixel location. For explanatory purposes, three variants of the proposed method are presented and evaluated. A ground-truth image set, in which RGB channels were not obtained by demosaicking, is subsampled in a Bayer CFA pattern to produce mosaicked images for testing. In varying densities, SPN is introduced to these Kodak images for method and apparatus evaluation. Results of the proposed method and its variants are compared with those obtained with MATLAB’s demosaic function. Considering the alternatives and also apparatus complexity, the proposed nonlinear demosaicking method proves superior in visual quality, for smooth textures and along edges, and in peak signal-to-noise ratio, when there is low-density SPN.

Combined thermographic phosphor and digital image correlation (TP + DIC) for simultaneous temperature and strain measurements

AbstractThermographic phosphors (TP) are combined with stereo digital image correlation (DIC) in a novel diagnostic, TP + DIC, to measure full‐field surface strains and temperatures simultaneously. The TP + DIC method is presented, including corrections for nonlinear CMOS camera detectors and generation of pixel‐wise calibration curves to relate the known temperature to the ratio of pixel intensities between two distinct wavelength bands. Additionally, DIC is employed not only for strain measurements but also for accurate image registration between the two cameras for the two‐colour ratio method approach of phosphoric thermography. TP + DIC is applied to characterize the thermo‐mechanical response of 304L stainless steel dog bones during tensile testing at different strain rates. The dog bones are patterned for DIC with Mg3F2GeO4:Mn (MFG) via aerosol deposition through a shadow mask. Temperatures up to 425°K (150°C) and strains up to 1.0 mm/mm are measured in the localized necking region, with conservative noise levels of 10°K and 0.01 mm/mm or less. Finally, TP + DIC is compared to the more established method of combining infrared (IR) thermography with DIC (IR + DIC), with results agreeing favourably. Three topics of continued research are identified, including cracking of the aerosol‐deposited phosphor DIC features, incomplete illumination for pixels on the border of the phosphor features, and phosphor emission evolution as a function of applied substrate strain. This work demonstrates the combination of phosphor thermography and DIC and lays the foundation for further development of TP + DIC for testing in combined thermo‐mechancial environments.

Efficient Pipelined Circuits for Histogram-based Tone Mapping of Nonlinear CMOS Image Sensors

Abstract Tone mapping is extensively researched to address the issue of displaying high dynamic range (DR) scenes on low DR displays. Even though several tone-mapping operators (TMOs) exist, not all are designed for hard real time. The operator has to be capable of scaling up the spatial resolution without compromising the frame rate. The implementation of a TMO should also be simple enough to embed in low-cost platforms for imaging systems. A computationally efficient, and well accepted, class of TMOs are global ones based on histograms. This work presents a method to implement TMOs that use histograms. This method is suitable for low-cost field-programmable gate arrays (FPGAs), using simple components such as adders, multipliers, and random access memories, and is particularly suited for a nonlinear CMOS image sensor (CIS) operating continuously in hard real time. The authors develop a fixed-point design, validated in bit-true fashion using Xilinx and Altera tools, from a background algorithm implemented using Matlab. Our generic design uses pipelined circuits and operates with low latency. The use of a hardware description language to model our circuits guarantees portability and modularity. Moreover, the complete TMO is generated from design parameters and a design template. The architecture is robust and scales well from kilopixel to megapixel formats. The circuits achieve 30 frames per second, at high definition resolutions, while occupying only a small fraction of the available logic elements in a low-cost FPGA device.

Spline-based colour correction for monotonic nonlinear CMOS image sensors

Nonlinear CMOS image sensor (CIS) technology is capable of high/wide dynamic range imaging at high frame rates without motion artifacts. However, unlike with linear CIS technology, there is no generic method for colour correction of nonlinear CIS technology. Instead, there are specific methods for specific nonlinear responses, e.g., the logarithmic response, that are based on legacy models. Inspired by recent work on generic methods for fixed pattern noise and photometric correction of nonlinear sensors, which depend only on a reasonable assumption of monotonicity, this paper proposes and validates a generic method for colour correction of nonlinear sensors. The method is composed of a nonlinear colour correction, which employs cubic Hermite splines, followed by a linear colour correction. Calibration with a colour chart is required to estimate the relevant parameters. The proposed method is validated, through simulation, using a combination of experimental data, from a monochromatic logarithmic CIS, and spectral data, reported in the literature, of actual colour filter arrays and target colour patches.

System-on-Chip design flow for the image signal processor of a nonlinear CMOS imaging system

System-on-Chip design flow for the image signal processor of a nonlinear CMOS imaging system

Digital Circuit Methods to Correct and Filter Noise of Nonlinear CMOS Image Sensors

Digital Circuit Methods to Correct and Filter Noise of Nonlinear CMOS Image Sensors

Modeling of CMS‐based nonuniform interconnects using FDTD technique

SummaryThis paper presents the finite‐difference time‐domain model of nonuniform interconnects including skin effect losses based on the current mode signaling (CMS). For accurate analysis, the nonlinear CMOS inverter is used as a driver for coupled nonuniform interconnects. These effects are incorporated in the proposed model using the modified alpha power law model. Additionally, high‐frequency losses are incorporated in the proposed model that further improves the accuracy. Using the proposed model, the performance of nonuniform interconnects is investigated using the CMS scheme. Time‐domain analysis model is derived from CMS nonuniform interconnects using finite‐difference time‐domain technique. Both inductive and capacitive couplings have been considered to incorporate coupling effects in interconnects. The efficiency of CMS interconnects is evaluated by comparing with conventional voltage mode signaling interconnects. The propagation delays and dynamic and functional cross talk effects at the far end of the coupled nonuniform interconnect are analyzed at the 32‐nm technology node. The proposed model results are validated using the standard HSPICE simulations.

Modeling and sizing of non-linear CMOS analog circuits used in mixed signal systems

In this paper, modeling of performance parameters and time efficient yet accurate sizing methodology of CMOS analog non-linear circuits have been proposed. The proposed modeling methodology generates empirical models of the non-linear circuit performance parameters in monomial or posynomial form, which is geometric programming (GP) compatible, as a function of the final design variables of the circuit (i.e. the width and length of the transistors). The proposed non-linear circuit sizing methodology, referred to as iterative geometric programming utilizes a correction factor for each of the GP compatible performance parameter models. These correction factors are updated using SPICE simulation after every iteration of the GP optimization. The proposed methodology takes advantage of GP optimization and at the same time it uses SPICE simulation to improve the design point by rectifying inaccuracies that may exists in the GP compatible performance models. Both the proposed methodologies have been validated in a 0.18 μm CMOS technology. The dynamic comparator and the bootstrap switch which are commonly used non-linear circuits in analog-mixed signal systems, have been used as the example circuits. It has been observed that the proposed sizing algorithm converges rapidly and give final design point with SPICE level accuracy higher than 99 %. The efficiency and the accuracy of the proposed algorithm has been numerically compared w.r.t. the sizing algorithm using evolutionary algorithm. It has been observed that the proposed algorithm gives much better results. Moreover, the proposed algorithm is hundreds times faster than that of the evolutionary algorithm.

Diagnosis of a soft short and local variations of parameters occurring simultaneously in analog CMOS circuits

This paper is devoted to fault diagnosis of nonlinear analog CMOS circuits designed in nanometer technology. A method that allows diagnosing a single soft short and local parameter variations, occurring simultaneously, is developed. The method exploits DC measurements at limited number of points in the test phase. The diagnostic test leads to a system of nonlinear algebraic equations, not given in explicit analytical form, that may have multiple solutions. The solutions determine the sets comprising one soft short value and several values of the preliminary selected parameters. To find them an extended simplicial algorithm is developed. It allows tracing different space curves, leading to different solutions. Moreover, a procedure for selecting the actual solution from among the obtained ones is proposed. For illustration a representative numerical example is discussed in detail.

Generation of coherent supercontinuum in a-Si:H waveguides: experiment and modeling based on measured dispersion profile.

Hydrogenated amorphous silicon (a:Si-H) has recently been recognized as a highly nonlinear CMOS compatible photonic platform. We experimentally demonstrate the generation of a supercontinuum (SC) spanning over 500 nm in a-Si:H photonic wire waveguide at telecommunication wavelengths using femtosecond input pulse with energy lower than 5 pJ. Numerical modeling of pulse propagation in the waveguide, based on the experimentally characterized dispersion profile, shows that the supercontinuum is the result of soliton fission and dispersive wave generation. It is demonstrated that the SC is highly coherent and that the waveguides do not suffer from material degradation under femtosecond pulse illumination. Finally, a direct comparison of SC generation in c-Si and a-Si:H waveguides confirms the higher performances of a-Si:H over c-Si for broadband low power SC generation at telecommunication wavelengths.

An output code offset-free comparator for SAR ADCs based on non-linear preamplifier and CMOS inverters

The Tanh transfer function of the differential pair operating in weak inversion is employed to implement the non-linear pre-amplification for the comparator of the SAR ADC. This non-linear preamplifier achieves a low gain for large input signals therefore the comparator can operate at a full speed (overdrive-free), while the high gain it achieved for small input signals improves the accuracy of the comparator. By combining the non-linear preamplifier and CMOS inverters, the issue of the comparison point shift in CMOS inverter due to fabrication process can be neglected, providing an output code offset-free solution. Simulations for the most critical zero-crossing overdrive cases for a 12-bit SAR ADC demonstrated that by cascading four stage differential pairs, the gain difference between the input signals of (1/2)LSB and (1/4)Vref is 49dB, while the output of the preamplifier for the input of (1/2)LSB is big enough to tackle the comparison point shift in the following comparison stage. Fabricated using the 0.35μm AMS CMOS technology, the comparator occupied an area of 130×140μm2 while consuming 6.2μW of power under a 1.5V single power supply which is suitable for low-power applications. Chip tests demonstrated that the fabricated chips achieved 12-bit resolution without offset when working at 100KSPS. This pure analog comparator could lead to higher resolution or higher speed by cascading more stages of the non-linear pair or by applying more current in the last stage of the non-linear pair.

Design of nonlinear CMOS circuits in the Nano-GHz Era and its mathematical challenges

Abstract Modern communication systems are working on industrial, scientific and medical (ISM) radio frequency (RF) bands. Today most research and development activities in industrial companies and universities are concentrated to frequency bands between 1 GHz and 24 GHz up to 60 GHz. For the construction of mixed-signal chips for cellular telephones and other wireless LAN applications (Bluetooth, HIPERLAN, etc.) different semiconductor technologies are used. In order to combine analogue functionality for the RF front end and digital functionality for high-speed signal processing nonlinear circuit concepts must be used and CMOS technology has to be applied. In order to construct high-quality RF transceiver chips a submicron CMOS technology (180 nm and below) is needed. Therefore we come into the Nano-GHz Era of circuit design. In this work corresponding mathematical challenges of modern RF CMOS design of transceiver circuits, with a focus on oscillator circuits, are discussed. It is shown that these circuits can be modelled as dynamical systems and their environment and their devices by partial differential equations. For circuit design aspects bifurcation theory and other mathematical concepts from dynamical systems as well as advanced numerical methods can be applied in order to build up an efficient design system for these RF CMOS circuits. In this paper some key aspects of future circuit design will be presented and discussed.

Low-Voltage CMOS Nonlinear Transconductors and Their Application to Companding Current-Mode Filters

Two novel nonlinear CMOS transconductors that can be employed for building CMOS current-mode filters are presented and their performances compared to formerly proposed topologies aimed at the same goal. The first one is based on a previous topology proposed by the authors, where a new biasing procedure leads to an improved performance for low supply voltages. The second one follows a novel approach, based on cascading a transresistor and a transconductor. The analysis is complemented with a more general approach based on the identification of translinear loops present in the circuit. Both nonlinear transconductors can operate at supply voltages as low as one V GS plus two V DS of a saturated MOSFET. CMOS current-mode filters based on these blocks are built following companding techniques, and their correct operation is validated by simulation and experimental results.

Crosstalk of microstrip lines with capacitor loads

Recently, the high integration of electrical circuits and the use of highly sensitive elements cause problems such as crosstalk and malfunction in data transmission equipment. It is important to study the cause of crosstalk, identify it, and suppress it. The loads of microstrip lines are usually composed of nonlinear components, such as CMOS logic circuits in an actual circuit. To simplify the nonlinearity, a linear load of a capacitor regarding the nonlinear CMOS device as a variable capacitor dependent on voltage is used. We measured the far-end crosstalk by changing the capacitance value of capacitive loads and simulated using the 4- port network.

Nonlinear switched-current CMOS IC for random signal generation

A nonlinear switched-current circuit is presented that implements a chaotic algorithm for the generation of broadband, white analogue noise. The circuit has been fabricated in a double-metal, single-poly 1.6μm CMOS technology and uses a novel, highly accurate CMOS circuit strategy to realise piecewise-linear characteristics in the current-mode domain. Measurements from the silicon prototype show a flat spectrum from DC to ∼30% of the clock frequency, for a clock frequency of 500kHz.

Comment on "A nonlinear CMOS analog cell for VLSI signal and information processing"

For original paper see Khachab et. al., ibid., vol.26, p.1689 (1991) In the title paper, a reference to Tsividis et. al. (1986) has been given following the mention of the four-MOSFET, crosscoupled, triode-operated transconductor with two control voltages. To avoid the possibility of misunderstanding on the part of readers, we would like to state that we were not involved in the invention of this circuit (which is to be distinguished from its two-transistor precursor). This circuit was made known to us in April 1985 by Z.Czamul. He proposed the above four transistor circuit, detailed its several advantages, and laid the foundations for its use in several ways. >

A nonlinear CMOS analog cell for VLSI signal and information processing

A simple reconfigurable continuous-time nonlinear CMOS building block for analog VLSI applications is presented. The new block is introduced as a basic analog cell for the implementation of analog VLSI systems. It simultaneously achieves four-quadrant multiplication and division. Its applications in both analog signal and information processing are discussed. These include multiplication, signal squaring, division, signal inversion, amplitude modulation, RMS-DC conversion, and neural computing. Using the new cell, a MOS VLSI implementation of a feedback/feedforward neural network is developed which achieves the scalar product of two n-tuple vectors by 4(n+1) MOS transistors and one operational amplifier. To verify the versatility of the new cell and its applications, experimental results obtained from a test chip that was fabricated using the MOSIS 2- mu m CMOS process are included.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Logarithmic and exponential switched-capacitor convertors and some of their applications

The paper is devoted to the design of nonlinear analogue CMOS switched-capacitor (SC) circuits which realise logarithmic and/or exponential transfer characteristics. Some new circuit arrangements for SC logarithmic exponential convertors and exponential time-function generators are presented. Details of implementation and experimental test results are also given.