Nonvolatile Flash Research Articles

The charge storage characteristics of ZrO2 nanocrystallite-based charge trap nonvolatile memory

ZrO2 nanocrystallite-based charge trap flash memory capacitors incorporating a (ZrO2)0.6(SiO2)0.4 pseudobinary high-k oxide film as the charge trapping layer were prepared and investigated. The precipitation reaction in the charge trapping layer, forming ZrO2 nanocrystallites during rapid thermal annealing, was investigated by transmission electron microscopy and X-ray diffraction. It was observed that a ZrO2 nanocrystallite-based memory capacitor after post-annealing at 850 °C for 60 s exhibits a maximum memory window of about 6.8 V, good endurance and a low charge loss of ∼25% over a period of 10 years (determined by extrapolating the charge loss curve measured experimentally), even at 85 °C. Such 850 °C-annealed memory capacitors appear to be candidates for future nonvolatile flash memory device applications.

Flexible Nonvolatile Transistor Memory Devices Based on One‐Dimensional Electrospun P3HT:Au Hybrid Nanofibers

AbstractA novel flexible nonvolatile flash transistor memory devices on polyethylene naphthalate (PEN) substrate using 1D electrospun nanofiber of poly(3‐hexylthiophene) (P3HT):gold nanoparticles (Au NPs) hybrid as the channel is presented. The Au NPs are functionalized with self‐assembled monolayer (SAM) of para‐substituted amino (Au‐NH2), methyl (Au‐CH3) or trifluoromethyl (Au‐CF3) tail groups on the benzenethiol moiety. They are employed as localized charge traps across the nanofiber channel and program/erase the device towards low conductance (OFF)/high conductance (ON) states under the applied electrical field. With the low operation voltage of ±5 V, the hybrid nanofiber transistor memories exhibit a 3.5–10.6 V threshold voltage shifting and at least 104 s data retention, with a minimum effect on ≈100 programmed/erased stress endurances. The dipoles of the SAM probably modify the work function of the Au NPs associated with the P3HT nanofiber channel and manifest the degree of negative threshold voltage shifting in an order of Au‐NH2 > Au‐CH3 > Au‐CF3. The devices remain reliable and stable even under the bending conditions (radius: 5–30 mm) or 1000 repetitive bending cycles. The hybrid nanofiber can be used to obtain high‐performance digital nanoscale memories for flexible high density data storage devices.

MRT-PLRU: A General Framework for Real-Time Multitask Executions on NAND Flash Memory

This paper proposes a novel technique called mRT-PLRU (Multitasking Real-Time constrained combination of Pinning and LRU), which forms a generic framework to use inexpensive nonvolatile NAND flash memory for storing and executing real-time programs in multitasking environments. In order to execute multiple real-time tasks stored in NAND flash memory with the minimal usage of expensive RAM, the mRT-PLRU is optimally configured in two steps. In the first step, the per-task analysis finds the function of RAM size versus execution time (and the corresponding optimal pinning/LRU combination) for each individual task. Using these functions for all the tasks as inputs, the second-step called a stochastic-analysis-in-loop optimization conducts an iterative convex optimization with the stochastic analysis for the probabilistic schedulability check. As a result, the optimization loop can optimally determine the RAM sizes for multiple tasks such that their deadlines are probabilistically guaranteed with the minimal size of total RAM. The usefulness of the developed technique is intensively verified through both simulation and actual implementation. Our experimental study shows that mRT-PLRU can save up to 80 percent of RAM required by the industry-common shadowing approach.

Implementation of Product Reed Solomon Codes for Multi level cell Flash controller

In recent years, multi-level cell (MLC) flash memories have been developed as an effective solution for increasing the storage density and reducing the cost of flash memories. MLC flash memories are especially for NAND flash memories . Error control coding (ECC) is essential for correcting errors in Flash memories.In order to correct multiple random errors and burst errors, an efficient decoding algorithms are required.In this work (255, 231) Product Reed-Solomon (RS) code technique for non-volatile NAND flash memory system sare used. In this proposed code that is Product Reed Solomon can correct both multiple random errors and burst errors. The Product Reed Solomon code consists of two shortened Reed-Solomon codes and a conventional Reed- Solomon code. It can correct up to certain symbol errors. A simulation result shows that the code has improved the coding gain and low power consumption.

Professor Fujio Masuoka?s Passion and Patience Toward Flash Memory

The main feature of Flash Memory is that it can retain data when the power is shut down, which is an indispensable part of a modern electronic system. System designers benefited greatly when the electrically erased and programmed nonvolatile Flash Memory became available. DRAM has been mainly used for the main memory to store the data and program in the computer. DRAM is fast, however, it can no longer retain data when the power is shut down. It is called a volatile memory. Therefore, personal computers have external storage devices of Hard Disk Drive (HDD) at any cost. This replacement of HDD by Flash Memory has been just got started. Flash Memory has a variety of advantages; low cost, light, low power (eco-friendly), vibration free, and resistant to moisture, etc. These good points of Flash Memory have innovatively produced a digital camera, cellular phone, and removal storage card. And now, Solid State Disk (SSD) has been fed directly into a computer in the replacement of HDD.

Hindrance-functionalized π-stacked polymer based on polystyrene with pendent cardo groups for organic electronics

A hindrance-functionalized π-stacked polymer, poly(4-(9-phenyl-fluoren-9-yl)styrene) (PPFS), was designed and synthesized by the introduction of bulky 9-phenylfluorenyl moieties (PFMs) with 3D cardo structure into all the phenyl units of polystyrene (PS) through the sp3 carbon linkage. The PFMs obviously alter π-stacked conformation and interchain interactions with respect to the precursor PS. The suitable HOMO–LUMO energy gap, high triplet energy, and excellent thermal and morphological stabilities enable PPFS to serve as not only electrically bistable materials but also phosphorescent hosts. Memory devices using PPFS as an active layer exhibited nonvolatile flash memory performance with ON/OFF current ratio up to 104, high stability in retention time up to 104 s and a number of read cycles up to 105 under a read voltage of 1.5 V in both ON and OFF states, while PS based devices exhibited no memory performance. Polymer light-emitting devices (PLEDs) using PPFS as the host and FIrpic as the guest exhibited blue emission with CIE chromaticity coordinates (x, y) of (0.146, 0.349). These results indicate that hindrance-functionalization opens a way to transform commercially available general purpose polystyrenes into functional π-stacked macromolecules.

Thermally stable memory devices using graphene flakes sandwiched polymethyl methacrylate polymer layers

Fabrication and characterization of graphene flakes sandwiched polymethyl methacrylate (PMMA) hybrid bistable devices (HBD) is reported in this paper. Graphene flakes (GFs) sandwiched polymer layers were prepared through a simple solution process. The fabricated memory devices have exhibited remarkable electrical bistable behavior even at 150°C. Bistable memory behavior of the fabricated devices have been described on the basis of current-voltage characteristics. Reasonably good ON/OFF current ratio (∼103) and retention property have been obtained from the constructed memory devices. The device showed excellent stability up to 105 switching cycles without any degradation both in ON and OFF states. The results obtained have indicated that the HBD fabricated by embedding graphene flakes in an insulating polymer matrix have potential applications in organic nonvolatile flash memory devices.

Charge storage properties of InP quantum dots in GaAs metal-oxide-semiconductor based nonvolatile flash memory devices

Metal organic vapor phase epitaxially grown 5 nm InP quantum dots (QDs) were embedded as charge storage elements between high-k control and tunneling dielectric layers in GaAs metal-oxide-semiconductor based nonvolatile memory devices. The QDs trap more electrons resulting in a large memory window (6.3 V) along with low leakage due to Coulomb blockade effect. 16.5% charge loss was found even after 105 s indicating its good charge storing potential. The programming and erasing operations were discussed with proposed band diagram.

Charge redistribution in a charge storage layer containing C60 molecules and organic polymers for long electron retention

A gate stack structure with an organic-polymer tunneling gate insulator on a C60-containing organic-polymer layer was developed for use as nonvolatile flash memory. Examination of the memory characteristics revealed substantial flatband voltage shifts for both electron and hole injections into C60 molecules. A long retention time was obtained for electron injection. Charge redistribution phenomena were observed in the electron retention characteristics immediately after the bias application was terminated. This proposed stack structure of organic polymers opens the door to the development of inexpensive electronic memories.

Radically Enhanced Molecular Switches

The mechanism governing the redox-stimulated switching behavior of a tristable [2]rotaxane consisting of a cyclobis(paraquat-p-phenylene) (CBPQT(4+)) ring encircling a dumbbell, containing tetrathiafulvalene (TTF) and 1,5-dioxynaphthalene (DNP) recognition units which are separated from each other along a polyether chain carrying 2,6-diisopropylphenyl stoppers by a 4,4'-bipyridinium (BIPY(2+)) unit, is described. The BIPY(2+) unit acts to increase the lifetime of the metastable state coconformation (MSCC) significantly by restricting the shuttling motion of the CBPQT(4+) ring to such an extent that the MSCC can be isolated in the solid state and is stable for weeks on end. As controls, the redox-induced mechanism of switching of two bistable [2]rotaxanes and one bistable [2]catenane composed of CBPQT(4+) rings encircling dumbbells or macrocyclic polyethers, respectively, that contain a BIPY(2+) unit with either a TTF or DNP unit, is investigated. Variable scan-rate cyclic voltammetry and digital simulations of the tristable and bistable [2]rotaxanes and [2]catenane reveal a mechanism which involves a bisradical state coconformation (BRCC) in which only one of the BIPY(•+) units in the CBPQT(2(•+)) ring is oxidized to the BIPY(2+) dication. This observation of the BRCC was further confirmed by theoretical calculations as well as by X-ray crystallography of the [2]catenane in its bisradical tetracationic redox state. It is evident that the incorporation of a kinetic barrier between the donor recognition units in the tristable [2]rotaxane can prolong the lifetime and stability of the MSCC, an observation which augurs well for the development of nonvolatile molecular flash memory devices.

Performance Evaluation of the MOHOS Flash Memory with Fluorinated HfO2 Charge Storage Layer Using Gate Fluorine Ion Implantation

Electrical characteristics improvement of the fluorinated metal/SiO2/HfO2/SiO2/Si (MOHOS) flash memory using gate fluorine ion implantation (GFI) process has been investigated. Si-F or Hf-F bonds formation due to fluorine incorporation can reduce undesirable charges trapping and leakage path creation in the tunneling oxide, which consequently increases the program/erase (P/E) speed and endurance. Moreover, fluorinated flash memory not only enhances P/E efficiency, but also improves the data retention characteristic, which can be explained by more deep-level traps and reduced leakage path due to fluorine incorporation. P/E window closure during endurance stressing is significantly suppressed for the fluorinated flash memory, which can be also ascribed to stronger Si-F or Hf-F bonds formation within the dielectrics due to fluorine incorporation. However, the fluorinated MOHOS flash memory clearly exhibits apparent erase-saturation phenomenon due to higher electric field across on blocking oxide. The results clearly indicate the fluorinated flash memory using GFI process to simultaneously fabricate fluorinated OHO dielectrics becomes a feasible technology for future MOHOS-type nonvolatile flash memory application.

Nanoscale 2-Bit/Cell HfO$_{\bf 2}$ Nanocrystal Flash Memory

In this paper, we demonstrate 50-nm trigate nonvolatile HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> nanocrystal memory devices on silicon-on-insulator wafers. The proposed technique, which is fully compatible with current CMOS technologies, is used to form highly localized HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> nanocrystals for application in nonvolatile flash memory. We successfully scale down conventional nonvolatile floating gate memories below the 50-nm node to achieve nanodevices for application in next-generation nonvolatile memories.

Stacked Gated Twin-Bit (SGTB) SONOS Memory Device for High-Density Flash Memory

A novel stacked gated twin-bit SONOS memory for high-density nonvolatile flash memory is introduced. We introduced gated twin-bit (GTB) memory previously that has a cut-off gate and two memory nodes at a single wordline. To increase the density of the GTB memory integration, we stacked poly-silicon gates in a vertical direction. In a 4F <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^2$</tex></formula> size, we can integrate 2 N memory nodes, where N is the number of stacked gates. In this paper, its fabrication method is introduced and electrical characteristics are investigated thoroughly by device simulations.

Conjugated polymers with cationic iridium(iii) complexes in the side-chain for flash memory devices utilizing switchable through-space charge transfer

Polycarbazole and polyfluorene containing cationic iridium(III) complexes in the side-chain have been designed and synthesized. Both polymers have been demonstrated to show conductance switching behavior and non-volatile flash memory devices based on them were successfully realized, in which the formation and dissociation of through-space charge-transfer states from the conjugated polymer “sea” to the Ir(III) complex “island”, controlled by voltage, are responsible for the conductance switching behavior and memory effect. The devices exhibit low reading, writing, and erasing voltages and a high ON/OFF current ratio. Both ON and OFF states are stable up to 107 read cycles at a read voltage of −1.0 V. Due to the different chemical structures of the polymer main-chain, the two devices show different threshold voltages. The polycarbazole derivative exhibits higher HOMO and LUMO levels compared with the polyfluorene analogue. Thus, the threshold voltage from the OFF to ON state of the device based on the polycarbazole derivative is obviously lower than that of the polyfluorene derivative-based device because of the low energy barrier between the work function of the ITO anode and the HOMO level of the polycarbazole derivative. Similarly, the threshold voltage from the ON to OFF state is evidently higher because the energy barrier of electron injection from Al into the LUMO of the polycarbazole derivative is slightly higher than that of the polyfluorene analogue. Thus, the threshold voltages of memory devices may be rationally modulated by modifying the chemical structure of polymers.

Comparison of Fluorinated HfO2 and Si3N4 Charge Trapping Layer for Nonvolatile Flash Memories

Characteristics of fluorinated metal/SiO2/HfO2/SiO2/Si (F-MOHOS) and fluorinated metal/SiO2/Si3N4/SiO2/Si (F-MONOS) flash memory using gate fluorine ion implantation (GFI) have been investigated. Since dielectric constant of HfO2 is larger than Si3N4, electric field across on tunneling oxide of F-MOHOS flash memory is larger than F-MONOS flash memory, which results in faster program/erase speed. Moreover, HfO2 exhibits larger effective trapping density than Si3N4, which also contributes to faster program/erase speed for the F-MOHOS flash memory. Besides, charge retention of the F-MOHOS flash memory is superior than the F-MONOS flash memory, primarily due to larger conduction band offset at the HfO2/SiO2 interface (ΔEC = 1.7–2.0 eV) than at the Si3N4/SiO2 interface (ΔEC = 1.1 eV). F-MOHOS flash memory also exhibits superior program/erase endurance than F-MONOS flash memory. Therefore, F-MOHOS flash memory using GFI process is proposed to be suitable for future nonvolatile flash memory applications. On the other hand, larger dielectric constant of HfO2 inevitably induces larger electric field across on blocking oxide of F-MOHOS flash memory, then enhances electron back-tunneling from the gate electrode during erase operation, which results in obvious erase-saturation.

Macroscopic high density nanodisc arrays of zinc oxide fabricated by block copolymer self-assembly assisted nanoimprint lithography

We report a facile means of creating nanodisc arrays of ZnO with high densities (∼22 Gbit in−2) and narrow distributions in size, shape and periodicities (<15%) using a combination of block copolymer self-assembly and nanoimprint lithography (NIL). ZnO nanodisc arrays with sub-100 nm spatial resolutions, using high-throughput and manufacturing compatible approaches are realized. The fabrication combines benefits from the use of NIL, which is a high-throughput and repeatable tool and from the use of block copolymer self-assembly which provides for low-cost production of high-resolution NIL molds. Preliminary results of the investigation of memory performance of these arrays within MOS capacitor devices show a flat-band voltage shift of 2.53 V at a relatively low operating voltage of 10 V. A high charge trap density of 2.3 × 1018 cm−3 combined with excellent retention of ∼80% after 1000 s of discharging is observed with low tunnelling oxide thickness of 3 nm, demonstrate significant promise of the ZnO nanodiscs to act as charge storage centers in non-volatile flash memory devices.

A poly(fluorene-thiophene) donor with a tethered phenanthro[9,10-d]imidazole acceptor for flexible nonvolatile flash resistive memory devices

A conjugated poly(fluorene-thiophene) donor and a tethered phenanthro[9,10-d]imidazole acceptor (PFT-PI) was used as the active layer in flexible nonvolatile resistor memory devices with low threshold voltages (±2 V), low switching powers (∼100 μW cm(-2)), large ON/OFF memory windows (10(4)), good retention (>10(4) s) and excellent endurance against electric and mechanical stimulus.

Low-voltage driving solution-processed nickel oxide based unipolar resistive switching memory with Ni nanoparticles

Resistive random access memory (RRAM) combines the advantages of nonvolatile flash memory and volatile dynamic random access memory, avoiding their drawbacks. For the practical use of RRAM, achieving low-voltage driving is strongly desired. Here we report the effect of Ni nanoparticles on solution-processed NiO based RRAM which can realize a one diode one resistor operation by unipolar resistive switching mode and low-voltage driving for future demands. The Ni nanoparticles not only contributed to high oxygen mobility, but also affected effective insulator thickness reduction, and stoichiometric variation in NiO thin films. Furthermore, the Ni nanoparticle embedded device demonstrated good reliability. These findings can enhance the applicability of RRAM as a next generation memory device.

Electronic structure of silicon oxynitride: Ab-initio and experimental study, comparison with silicon nitride

Amorphous silicon oxide SiO2, silicon nitride Si3N4, and silicon oxynitride SiOxNy are three key dielectrics in silicon devices. Implementation of nitrided oxide (oxynitride SiOxNy) as a gate dielectric in metal-oxide-semiconductor field effect transistors has been shown to significantly improve the reliability and lifetime of devices. Also, amorphous oxynitride is used as a tunnel dielectric in nonvolatile flash memory devices. The present paper is devoted to the experimental and theoretical study of silicon oxynitride electronic structure. The ionic formula of crystalline Si2N2O is deduced from the first principles. Effective masses of charge carriers in Si2N2O are calculated and compared with experimental data on tunnel injection in amorphous SiNxOy samples. Also experimental x-ray absorption and emission spectra are compared with the theoretically calculated ones.

Synthesis and memory characteristics of polyimides containing noncoplanar aryl pendant groups

A series of soluble aromatic polyimides were prepared from 2,2′-diphenyl-4,4′-biphenyl diamine (DPBD), 2,2′-bis(biphenyl)-4,4′-biphenyl diamine (BBPBD), 2,2′-bis[4-(naphthalen-1-yl)phenyl]-4,4′-biphenyl diamine (BNPBD) and 2,2′-bis(3,5-dimethoxyphenyl)-4,4′-biphenyl diamine (BMPBD) by polycondensation with 2,2′-bis[4′-(3′′,4′′,5′′-trifluorophenyl)phenyl]-4,4′,5,5′-biphenyl tetracarboxylic dianhydride via a two-step procedure. The resulting polymers were fully characterized and they exhibited excellent organosolubility, high thermal and dimensional stability. Resistive switching devices with the configuration of Al/polymer/ITO were constructed from these polyimides by using conventional solution coating process. Devices with the active layer based on DPBD, BBPBD and BNPBD exhibited nonvolatile and rewritable flash type memory characteristics with the turn-on voltage at −2.0 to −3.0 V and the turn-off voltage at 2.0–3.0 V. Whereas, device based on BMPBD demonstrated a bipolar write-once read-many times (WORM) memory capability with the writing voltage around ±3.0 V. The ON/OFF current ratio of these devices was of about 106 and the retention times can be as long as 104 s.