Nonvolatile Analog Memory Research Articles

Unsupervised Learning Using Charge-Trap Transistors

Unsupervised learning is demonstrated using a device ubiquitously found in today's technology: a transistor with high-k -metal gate. Specifically, the charge-trapping phenomenon in the high-k gate dielectric is leveraged so that the device can be used as a non-volatile analog memory. Experimental data from 22-nm silicon-on-insulator devices reveal that a charge-trap transistor possesses promising characteristics for implementing synapses in neural networks, such as very fine tunability, weight-dependent plasticity, and low power consumption. A proof-of-concept winner-takes-all neural network is simulated based on experimental data and perfect clustering is achieved within tens of training cycles. This means that the network can be trained for multiple times, and a larger system can be built. The robustness of the procedure to the device variation is also discussed.

(Invited) Unconventional Computing with Memristors

By now, there have been many demonstrations of resistive switching (“memristive”) devices based on organic, chalcogenide, transition metal-oxide and silicon materials and involving different physical switching mechanisms, such as phase-change transitions and modulation of the ionic concentration profiles by electrical and/or thermal forces. The conductance of some properly engineered memristors can be continuously tuned with relatively large electrical bias, and retained, effectively indefinitely, when small stress is applied. Such analog nonvolatile memory functionality combined with potentially very high device density, achieved by lateral scaling and/or monolithical vertical integration, enable many new exciting applications of memristors in neuromorphic and other types of computing. In my talk, I will review several such applications based on metal-oxide memristors which were a recent focus of my group. I will start with stateful material implication logic, which was originally suggested by HPL group. In our work, we showed that 3D version of this logic allows resolving Feynman grand challenge of implementing 8-bit adder in a volume smaller than 50-nm cube. I will then review our experimental work on memristor-based security primitives, in which we utilized device variations and their nonlinear I-Vs to demonstrate functionality and physical performance superior to those of conventional approaches. Finally, I will discuss Race Logic, a novel computing paradigm in which information is encoded in timing of the signals, so that a particular problem is mapped to a circuit with controllable memristor-based delay elements, and the solution is provided by measuring the time for the injected signals to propagate via circuit. Due to direct encoding of the computation to the underlying physics, Race Logic is extremely energy efficient for a variety of problems, such as bioinformatics and neurocomputing. I will conclude my talk with a summary on the device/material challenges, and potential future work, specific to the discussed applications.

Microstructure and dynamics of vacancy-induced nanofilamentary switching network in donor doped SrTiO3−x memristors

Donor doping of perovskite oxides has emerged as an attractive technique to create high performance and low energy non-volatile analog memories. Here, we examine the origins of improved switching performance and stable multi-state resistive switching in Nb-doped oxygen-deficient amorphous SrTiO3 (Nb:a-STOx) metal–insulator–metal (MIM) devices. We probe the impact of substitutional dopants (i.e., Nb) in modulating the electronic structure and subsequent switching performance. Temperature stability and bias/time dependence of the switching behavior are used to ascertain the role of substitutional dopants and highlight their utility to modulate volatile and non-volatile behavior in a-STOx devices for adaptive and neuromorphic applications. We utilized a combination of transmission electron microscopy, photoluminescence emission properties, interfacial compositional evaluation, and activation energy measurements to investigate the microstructure of the nanofilamentary network responsible for switching. These results provide important insights into understanding mechanisms that govern the performance of donor-doped perovskite oxide-based memristive devices.

A 25. 3 <inline-formula> <tex-math notation="LaTeX">$\mu$ </tex-math> </inline-formula>W at 60 fps <inline-formula> <tex-math notation="LaTeX">$240 \times 160$ </tex-math> </inline-formula> Pixel Vision Sensor for Motion Capturing With In-Pixel Nonvolatile Analog Memory Using CAAC-IGZO FET

Utilizing a c-axis-aligned crystalline oxide semiconductor-based FET, we have fabricated a vision sensor with in-pixel nonvolatile analog memory. The sensor realized normal image data capturing, captured differential data of a given reference frame, and retained the captured data for an extended time in each pixel. Moreover, the sensor realized normal global shutter image capturing and motion capturing by extracting differential images. This is performed using the captured data and depends on the presence or absence of differences between normal images and reference images. The sensor has three operating modes: an imaging mode, a motion capturing mode, and a wait mode. Importantly, power consumption is reduced by powering off circuit blocks that are in a standby state.

Memcapacitive Characteristics of Metal-Oxide-Semiconductor Capacitor Structures by Compositional Redistribution

Memcapacitive characteristics defined to be a memorized capacitance change has been recently suggested and experimentally demonstrated. Di Ventra et al. noted that the memcapacitive characteristics involve the capacitance change in metal-oxide resulting from microscopic geometry change or history-dependent permittivity change [1]. Wang et al. reported the memcapacitive characteristics in ionic transport through SiO2 conical nanopore in KCl solution caused by redistribution of mobile ions [2]. We previously reported the analog memcapacitive characteristics in pn junction diode structures [3]. The pn heterojunction with the assembly of n-type Fe2O3 nanoparticles having Pt core (called Pt-Fe2O3 core-shell nanoparticles) on p+-Si substrate exhibited gradually changing capacitance as repeating the application of voltage with respect to the polarity of voltage. The analog memcapacitive characteristics also emulated the biological synaptic potentiation and depression motions, which is indicative of potential application to neuromorphic devices as well as analog nonvolatile memory and circuits. Since the memcapacitive phenomenon exhibits the memorized capacitance change, the memcapacitor has a potential to modulate the forward and reverse current in diode structure through altering the barrier height and depletion width at the interface. Also, the memcapacitance can modulate the drain current in MOSFETs and TFTs as variable gate stack capacitor, named memcapacitor, which gives the functions of memory, logic, neuromorphic operation, and so on. In this presentation, we discuss the memcapacitive characteristics in metal-oxide-semiconductor (MOS) capacitor structure consisting of reactive electrode (Mo, Al) and hafnium oxide (HfOX) on n-type Si and indium-gallium-zinc-oxide (IGZO) semiconductor substrates. The capacitance-voltage curves exhibited sequentially changing capacitance as repeating the voltage sweeps. The saturation capacitance was decreased as repeating +V application, while the depletion capacitance was barely changed as –V application. Also, the capacitance-time curves disclosed the same tendency of capacitance change. On the other hand, the MOS structure with inert electrode (Pt) did not show the capacitance change. These memcapacitive behaviors were induced by the migration of oxygen ions between reactive electrodes (Mo, Al) and HfOX, which modulated the permittivity and effective capacitor area. These results demonstrated the memcapacitive characteristics in MOS structure through voltage-driven oxygen migration for the application to memory, logic, and neuromorphic devices. [1] M. Di Ventra, Y. V. Pershin, and L. O. Chua, Proc. IEEE 97 1717 (2009). [2] D. Wang, M. Kvetny, J. Liu, W. Brown, Y. Li, and G. Wang, J. Am. Chem. Soc. 134, 3651 (2012). [3] Y. J. Noh, Y.-J. Baek, Q. Hu, C. J. Kang, Y. J. Choi, H. H. Lee, and T.-S. Yoon, IEEE Trans. Nanotechnol. 14, 798 (2015)

History Erase Effect in a Non-Volatile Memristor

This work presents a detailed study of the nonlinear dynamics of a tantalum oxide memristor recently fabricated at Hewlett Packard Labs. Our investigations uncover direct current, quasi-static, and alternating current behavior of the nanodevice. A thorough study of the dynamics emerging in the nanoscale element under various input/initial condition combinations reveals a fundamental property of the tantalum oxide device, which was unnoticed so far. The initial condition has no effect on the steady-state operation of the memristor under non-zero input. This property, known as fading memory in system theory, implies the uniqueness of asymptotic behavior of the memristor. The progressive input-induced memory erase phenomenon is solely determined by the switching dynamics of the nanodevice, mathematically described by the state evolution function, which governs the rate of evolution of the memristor state. A constant-sign DC input will activate on or off switching dynamics only. Consequently, due to the limited on/off memductance ratio, the memristor will asymptotically attain a fully-conducting or highly-resistive state, irrespective of the initial condition. Most interestingly, under AC periodic excitations, it is the pronounced asymmetry in the state dependence of on and off switching processes which is at the basis of the reported history erase effect. It is important to point out that this novel fading memory phenomenon does not compromise the nonvolatile behavior of the nanostructure. In fact, despite the device may be stimulated so as to forget its past history, it still has a continuum of analog nonvolatile memory states.

Analog Memristive and Memcapacitive Characteristics of Pt-Fe2O3 Core-Shell Nanoparticles Assembly on p+-Si Substrate

Analog memristive and memcapacitive switching characteristics were investigated in Pt-Fe2O3 core-shell nanoparticles (NPs) assembly on p+-Si substrate. The Ti/NPs/p+-Si structure exhibited gradually changing resistance (memristive) and capacitance (memcapacitive) at the same time as repeating the application of voltage with respect to the polarity of voltage. As applying negative voltage at top Ti electrode, the resistance decreased and the capacitance increased due to the increase of diffusion capacitance at n-NPs/p+ -Si junction. On the other hand, applying the positive voltage increased resistance and decreased capacitance by increasing depletion width at the junction. The polarity-dependent resistance and capacitance changes are thought to be ascribed to the charging of the NPs assembly that alters the potential of the assembly. The concurrent analog memristive and memcapacitive characteristics also emulated the biological synaptic potentiation and depression motions, which is indicative of potential application to neuromorphic devices as well as analog nonvolatile memory and circuits.

Donor‐Induced Performance Tuning of Amorphous SrTiO3 Memristive Nanodevices: Multistate Resistive Switching and Mechanical Tunability

Metal–oxide valence‐change memristive devices are the key contenders for the development of multilevel nonvolatile analog memories and neuromorphic computing architectures. Reliable low energy performance and tunability of nonlinear resistive switching dynamics are essential to streamline the high‐density circuit level integration of these devices. Here, manipulation of room temperature‐synthesized defect chemistry is employed to enhance and tune the switching characteristics of high‐performance amorphous SrTiO3 (a‐STO) memristors. Substitutional donor (Nb) doping with low concentrations in the a‐STO oxide structure allows extensive improvements in energy requirements, stability, and controllability of the memristive performance, as well as field‐dependent multistate resistive switching. Evidence is presented that room temperature donor doping results in a modified insulator oxide where dislocation sites act as charge carrier modulators for low energy and multilevel operation. Finally, the performance of donor‐doped a‐STO‐based memristive nanodevices is showcased, with the possibility of mechanical modulation of the nonlinear memristive characteristics of these devices demonstrated. These results highlight the potential of donor‐doped a‐STO nanodevices for high‐density integration as analog memories and multifunctional alternative logic elements.

Fowler-Nordheim Tunneling Characterization on Poly1-Poly2 Capacitors for the Implementation of Analog Memories in CMOS 0.5 μmTechnology

The experimental results of the Fowler-Nordheim characterization using poly1-poly2 capacitors on CMOS ON Semi 0.5 μm technology are presented. This characterization allows the development, design, and characterization of a new current-mode analog nonvolatile memory. Experimental results of the memory cell architecture are presented and demonstrate the usefulness of the proposed architecture.

LMS algorithm for programming an analogue memory cell

This article presents the optimal performance of a nonvolatile analogue memory cell fabricated in 1.2 µm CMOS process, which is programmed using a LMS (least mean square) algorithm to implement an adaptive FIR filter used to identify an unknown signal. The memory cell is programmed to store and update the weight in the filter as charge in the floating gate of a pMOS transistor (FGMOS). Programming is linear using a pulse density modulation scheme by means of tunnelling and hot injection electrons. The behavior of the memory is included and programming method is developed. The LMS algorithm performed very well, and does not require the signal to be piecewise stationary, and requires no manual operation other than selection of the step-size of the adaptive parameter.

Programmable CMOS/Memristor Threshold Logic

This paper proposes a hybrid CMOS/memristor implementation of a programmable threshold logic gate. In this gate, memristive devices implement ratioed diode-resistor logic, while CMOS circuitry is used for signal amplification and inversion. Due to the excellent scaling prospects and nonvolatile analog memory of memristive devices, the proposed threshold logic is in-field configurable and potentially very compact. The concept is experimentally verified by implementing a 4-input symmetric linear threshold gate with an integrated circuit CMOS flip-flop, silicon diodes, and Ag/a-Si/Pt memristive devices.

Nonvolatile Analog Memory Transistor Based on Carbon Nanotubes and C60 Molecules

A nonvolatile analog memory transistor is demonstrated by integrating C60 molecules as charge storage molecules in the transistor gate, and carbon nanotubes (CNTs) in the transistor channel. The currents through the CNT channel can be tuned quantitatively and reversibly to analog values by controlling the number of electrons trapped in the C60 molecules. After tuning, the electrons trapped in the C60 molecules in the gate, and the current through the CNT channel, can be preserved in a nonvolatile manner, indicating the characteristics of the nonvolatile analog memory.

Embedded Analog Nonvolatile Memory With Bidirectional and Linear Programmability

Nonvolatile storage of analog values with floating-gate transistors has been useful for many applications. While most proposed analog nonvolatile memory devices employ electron tunneling to modify floating-gate charges, this brief presents an embedded analog nonvolatile memory device that employs only hot-carrier injections to achieve bidirectional programmability. Without using electron tunneling, the proposed circuit not only avoids multiplexing high-voltage signals but also facilitates direct storage of new data. In addition, each memory cell incorporates a simple inverter to make the programming process nearly linear, facilitating bidirectional and linear adaptability for neuromorphic systems. A prototype array of the analog memory has been fabricated with the standard CMOS 0.35- technology. The chip includes a simple on-chip comparator to program the analog memory accurately and automatically by negative feedback. The effective resolution is more than 8 bits over a dynamic range of 1.4 V. The intercell disturbance during programming and the data retention ability are also examined.

THE MEMORIZATION BEHAVIORS OF DIFFERENT MIOS STRUCTURES

In this chapter the various kinds of charge storage cells are discussed as a result of examining many samples with different structures. The C-V, I-V and R-V measurements of the structures confirm the memorization capability of MIOS devices. The examined structures reveal three kinds of memory actions. The first one is the charge storage capability which can be shown through (C-V) curve shifting as the device was exposed to certain stress for a certain time. The second is the electronic switching that is demonstrated by the fact that the switching between ON and OFF states and back to original state can only be obtained by inverting the polarity of the applied bias voltage. The third kind of memorization action is that the device can be switched into a variety of stable intermediate resistance states. The new resistance state is determined by the height of the programming pulse applied to the device. This memory action is noticed from R-V characteristic and known as a nonvolatile analogue memory behavior.

24.1: A Programmable Analog Reference Memory for Adaptive Gamma Correction

A CMOS Integrated Circuit stores multiple sets of gamma reference voltages in re-programmable non-volatile analog memory. Stored gamma curves are selected by simple address inputs, allowing adaptive correction of video content, color, ambient light, backlight or temperature. The device offers significant performance and cost advantages compared to competing solutions.

A 19.2 GOPS mixed-signal filter with floating-gate adaptation

We have built a 48-tap, mixed-signal adaptive FIR filter with 8-bit digital input and an analog output with 10 bits of resolution. The filter stores its tap weights in nonvolatile analog memory cells using synapse transistors, and adapts using the least mean square (LMS) algorithm. We run the input through a digital tapped delay line, multiply the digital words with the analog tap weights using mixed-signal multipliers, and adapt the tap coefficients using pulse-based feedback. The accuracy of the weight updates exceeds 13 bits. The total die area is 2.6 mm/sup 2/ in a 0.35-/spl mu/m CMOS process. The filter delivers a performance of 19.2 GOPS at 200 MHz, and consumes 20 mW providing a 6-mA differential output current.

A CMOS programmable analog memory-cell array using floating-gate circuits

The complexity of analog VLSI systems is often limited by the number of pins on a chip rather than by the die area. Currently, many analog parameters and biases are stored off-chip. Moving parameter storage on-chip could save pins and allow us to create complex programmable analog systems. In this paper, we present a design for an on-chip nonvolatile analog memory cell that can be configured in addressable arrays and programmed easily. We use floating-gate MOS transistors to store charge, and we use the processes of tunneling and hot-electron injection to program values. We have fabricated two versions of this design: one with an nFET injection mechanism and one with a pFET injection mechanism. With these designs, we achieve greater than 13-bit output precision with a 39-dB power-supply rejection ratio and no crosstalk between memory cells.

New Nonvolatile Analog Memories for Analog Data Processing

For the purpose of realizing a new intelligent system using mixed signal technology and its simplified VLSI implementation, we develop two new nonvolatile analog memories called “DTSDAM (dual tunnel SDAM)” and “FBSDAM (SDAM with feedback circuit)” based on “SDAM (switched diffusion analog memory)”. We fabricate these two analog memories using the 4 µm double-poly double-metal silicon technology developed for nonvolatile analog memories. We report the measurement results for the fabricated chips and estimate the performance of these new analog memories.

A Content-Addressable Memory Using Switched Diffusion Analog Memory with Feedback Circuit

For the purpose of realizing a new intelligent system and its simplified VLSI implementation, we propose a new nonvolatile analog memory called switched diffusion analog memory with feedback circui...

An electrically modifiable synapse array composed of metal-ferroelectric-semiconductor (MFS) FET's using SrBi/sub 2/Ta/sub 2/O/sub 9/ thin films

An array of metal-ferroelectric-semiconductor field effect transistors (MFSFETs) is fabricated on a silicon-on-insulator (SOI) structure using SrBi/sub 2/Ta/sub 2/O/sub 9/ as the gate insulator. It is demonstrated that each FET shows good characteristics as a nonvolatile analog memory due to partial polarization of the SrBi/sub 2/Ta/sub 2/O/sub 9/ film and that the array operates as an electrically modifiable synapse circuit for carrying out the weighted sum operation in an artificial neural network.