Unsupervised Learning Using Charge-Trap Transistors

Abstract

Unsupervised learning is demonstrated using a device ubiquitously found in today's technology: a transistor with high-k -metal gate. Specifically, the charge-trapping phenomenon in the high-k gate dielectric is leveraged so that the device can be used as a non-volatile analog memory. Experimental data from 22-nm silicon-on-insulator devices reveal that a charge-trap transistor possesses promising characteristics for implementing synapses in neural networks, such as very fine tunability, weight-dependent plasticity, and low power consumption. A proof-of-concept winner-takes-all neural network is simulated based on experimental data and perfect clustering is achieved within tens of training cycles. This means that the network can be trained for multiple times, and a larger system can be built. The robustness of the procedure to the device variation is also discussed.