Non-recurring Engineering Costs Research Articles

New High-Rate Timestamp Management with Real-Time Configurable Virtual Delay and Dead Time for FPGA-Based Time-to-Digital Converters

Modern applications require the ability to measure time events with high resolution, a full-scale range, and multiple input channels. Time-to-Digital Converters (TDCs) are a popular option to convert time intervals into timestamps. To reduce the time-to-market and Non-Recurring Engineering (NRE) costs, a Field-Programmable Gate Array (FPGA) implementation has been chosen. The high number of requested bits and channels, however, gives rise to routing congestion issues when routed in a parallel manner. In this paper, we will propose and analyze a novel solution, the Belt-Bus (BB), which involves a parallel-to-serial conversion of the timestamp stream coming from the TDC while maintaining chronological order and a sufficient high rate, and flagging the presence of timestamp overflow. Moreover, two new useful features are added. The first is a “Virtual Delay” to compensate for offsets due to cable length and FPGA routing path mismatch. The second is a “Virtual Dead-Time” to filter out unforeseen events. Finally, the BB was tested on a Xilinx 28 nm 7-Series Kintex-7 325T FPGA, achieving an overall data rate of 199.9 Msps with very limited resource usage (i.e., lower than a total of 4.5%), consuming only 480 mW in a 16-channel implementation.

Model-to-Circuit Cross-Approximation For Printed Machine Learning Classifiers

Printed electronics (PE) promises on-demand fabrication, low non-recurring engineering costs, and sub-cent fabrication costs. It also allows for high customization that would be infeasible in silicon, and bespoke architectures prevail to improve the efficiency of emerging PE machine learning (ML) applications. Nevertheless, large feature sizes in PE prohibit the realization of complex ML models in PE, even with bespoke architectures. In this work, we present an automated, cross-layer approximation framework tailored to bespoke architectures that enable complex ML models, such as Multi-Layer Perceptrons (MLPs) and Support Vector Machines (SVMs), in PE. Our framework adopts cooperatively a hardware-driven coefficient approximation of the ML model at algorithmic level, a netlist pruning at logic level, and a voltage over-scaling at the circuit level. Extensive experimental evaluation on 12 MLPs and 12 SVMs and more than 6000 approximate and exact designs demonstrates that our model-to-circuit cross-approximation delivers power and area optimal designs that, compared to the state-of-the-art exact designs, feature on average 51% and 66% area and power reduction, respectively, for less than 5% accuracy loss. Finally, we demonstrate that our framework enables 80% of the examined classifiers to be battery-powered with almost identical accuracy with the exact designs, paving thus the way towards smart complex printed applications.

An Optimized GIB Routing Architecture with Bent Wires for FPGA

Field-programmable gate arrays (FGPAs) are widely used because of the superiority in flexibility and lower non-recurring engineering cost. How to optimize the routing architecture is a key problem for FPGA architects because it has a large impact on FPGA area, delay, and routability. In academia, the routing architecture is mainly based on the connection blocks (CBs) and switch blocks (SBs), whereas most research has focused on SB architectures, such as Wilton, Universal, and Disjoint SB patterns. In this article, we propose a novel unidirectional routing architecture—general interconnection block (GIB)—to improve FPGA performance. With the GIB architecture, logic block (LB) pins can directly connect with the adjacent GIBs without programmable switches. Inside a GIB, LB pins can connect to the routing channel tracks on the four sides of a GIB. In particular, the logic pins from different neighboring LBs that connect to the same GIB can connect with each other with only one programmable switch. In addition, we enhance VTR to support the GIB with bent wires and develop a searching framework based on the simulated annealing algorithm to search for a near-optimal distribution of wire types. We evaluate the GIB architecture on VTR 8 with the provided benchmark circuits. The experimental results show that the GIB architecture with length-4 wires can achieve 9.5% improvement on the critical path delay and 11.1% improvement on the area-delay product compared to the VTR CB-SB architecture with length-4 wires. After exploring mixed wire types, the optimized GIB architecture can further improve the delay by 16.4% and area-delay product by 17.1% compared to the CB-SB architecture with length-4 wires.

AGILER: An Adaptive Heterogeneous Tile-Based Many-Core Architecture for RISC-V Processors

Tile-based many-core architectures are extensively used in modern system-on-chip designs to achieve scalable computing performance with adequate energy efficiency. Heterogeneity is the key element to boost computing performance and keep energy consumption under certain limits for several application domains. However, the steady increase of using many custom heterogeneous tiles leads to an expansion in design and integration cost with limited tiles re-usability. The recent widespread of open-source RISC-V ISA provides the potential to develop modular compute units that can be used for many application domains with high reduction in non-recurring engineering costs. The motivation of this work is to bring design modularity and adaptability features for heterogeneous tile-based many-core architectures by increasing their flexibility to realize different many-core configurations with less design time and costs. In this work, AGILER is proposed as an adaptive tile-base many-core architecture for heterogeneous RISC-V based processors. The proposed architecture consists of modular and adaptable heterogeneous multi-/single-core compute tiles that supports 32-/64-bit RISC-V ISAs with different memory hierarchies. Inter-tile communication is developed based on a scalable network-on-chip architecture to achieve a high degree of system scalability. AGILER supports run-time adaptation through a custom internal reconfiguration manager for dynamic and partial reconfiguration over Xilinx FPGAs. Evaluation results demonstrate that the proposed architecture features a scalable computing performance up to 685 MOPS for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8\times 32$ </tex-math></inline-formula> -bit tiles and 316 MOPS for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8\times 64$ </tex-math></inline-formula> -bit tiles with a scalable memory bandwidth up to 7.4 GB/s. AGILER is evaluated on Xilinx Virtex Ultrascale+ FPGA with a maximum reconfiguration time of 38.1 ms for a single compute tile.

SPECTRUM

Wireless communication standards such as Long-term Evolution (LTE) are rapidly changing to support the high data-rate of wireless devices. The physical layer baseband processing has strict real-time deadlines, especially in the next-generation applications enabled by the 5G standard. Existing basestation transceivers utilize customized DSP cores or fixed-function hardware accelerators for physical layer baseband processing. However, these approaches incur significant non-recurring engineering costs and are inflexible to newer standards or updates. Software-programmable processors offer more adaptability. However, it is challenging to sustain guaranteed worst-case latency and throughput at reasonably low-power on shared-memory many-core architectures featuring inherently unpredictable design choices, such as caches and Network-on-chip (NoC). We propose SPECTRUM , a predictable, software-defined many-core architecture that exploits the massive parallelism of the LTE/5G baseband processing workload. The focus is on designing scalable lightweight hardware that can be programmed and defined by sophisticated software mechanisms. SPECTRUM employs hundreds of lightweight in-order cores augmented with custom instructions that provide predictable timing, a purely software-scheduled NoC that orchestrates the communication to avoid any contention, and per-core software-controlled scratchpad memory with deterministic access latency. Compared to many-core architecture like Skylake-SP (average power 215 W) that drops 14% packets at high-traffic load, 256-core SPECTRUM by definition has zero packet drop rate at significantly lower average power of 24 W. SPECTRUM consumes 2.11× lower power than C66x DSP cores+accelerator platform in baseband processing. We also enable SPECTRUM to handle dynamic workloads with multiple service categories present in 5G mobile network (Enhanced Mobile Broadband (eMBB), Ultra-reliable and Low-latency Communications (URLLC), and Massive Machine Type Communications (mMTC)), using a run-time scheduling and mapping algorithm. Experimental evaluations show that our algorithm performs task/NoC mapping at run-time on fewer cores compared to the static mapping (that reserves cores exclusively for each service category) while still meeting the differentiated latency and reliability requirements.

Reconfigurable computing: toward software defined chips

With the rapid development of technology, software is rapidly evolving with emerging applications. Chips that fail to adapt to software (e.g., application-specific integrated circuits, ASICs) suffer from a short lifecycle and high nonrecurring engineering (NRE) costs. Meanwhile, as the projection of Moores law and Dennard scaling are decreasing, energy efficiency has shown a diminishing return with new technologies. The computing capacity of general-purpose processors is limited due to power budgets. Consequently, future chips must jointly optimize flexibility, power efficiency, and ease of programmability. Reconfigurable chips combine the high flexibility of a general-purpose processor and high energy efficiency of ASIC by providing on-demand customization of their architectures. This article thoroughly reviews the development and architecture of reconfigurable chips. Moreover, the future challenges of reconfigurable chips are analyzed. Based on these challenges, future directions are also discussed.

Agile and Open-Source Hardware

The thirteen articles in this special section focus on agile and open source hardware. These papers cover variety of research topics related to fast, agile, and open hardware design, including methodologies, languages, abstractions, and simulators. As the benefits f traditional technology scaling, like Dennard Scaling and Moore’s Law, slow significantly, computer architecture is poised to enter a golden age of innovation. Domain-specific architectures (DSA) are a promising solution to continue improving computing performance, while maintaining the level of energyand area-efficiency previously found in technology scaling. Unfortunately, traditional methodologies of chip design and hardware development have created significant barriers, requiring extremely high non-recurring engineering costs in tools, labor, IPs, and time, which ultimately hold back broad adoption of DSA.

Agile Hardware Development and Instrumentation With PyRTL

Domain-specific architectures have emerged as a promising solution to meet growing technology demands but with this comes an urgent need to improve hardware methodologies which often have long design cycles, rely on closed source and expensive tools, and have high nonrecurring engineering costs. In this article, we describe how our work developing PyRTL, an open source Python-based Hardware Development Toolkit, has proven to be a powerful agile hardware development and analysis tool with the features to improve current methodologies. We describe how this toolkit-driven approach encourages hardware reuse using modern object-oriented programming features and present an examination of its custom intermediate representation for hardware debugging, analysis, and instrumentation. This approach has proven useful in supporting fast design iteration in a variety of domains including cryptography and machine learning.

A review on embedded field programmable gate array architectures and configuration tools

Nowadays, systems-on-chip have reached a level where nonrecurring engineering costs have become a great challenge due to the increase of design complexity and postfabrication errors. Embedded field programmable gate arrays (eFPGAs) represent a viable alternative to overcome these issues since they provide postmanufacturing flexibility that can reduce the number of chip redesigns and amortize chip fabrication cost. In this paper, we present an overview on eFPGAs and their architectures, computer aided design (CAD) tools, and design challenges. An eFPGA must be well-designed and accompanied by an optimized CAD tool suite to respond to target application's requirements in terms of power consumption, area, and performance. In this survey, we studied coarse-grained eFPGAs with customized blocks which are used for domain-specific applications and fine-grained eFPGAs that are used for general purposes but have lower performance.

Towards a Modular RISC-V Based Many-Core Architecture for FPGA Accelerators

Multi-/Many-core architectures are emerging as scalable, high-performance and energy-efficient computing platforms suitable for a variety of application domains from edge to cloud computing. Recently, the appearance of RISC-V open-source ISA creates new possibilities to develop customized computing platforms with high savings in the non-recurring engineering costs. Moreover, the current trends toward open-source hardware frameworks are aimed to reduce design time and cost for complex system-on-chip architectures. Therefore, modularity and re-usability of hardware components are major challenges for flexible hardware architectures. The motivation behind this work is to introduce a modular cluster-based many-core architecture for FPGA accelerators that is re-usable and flexible tailored to implement different many-core taxonomies with less design time and costs by using regular and replicated sets of computing, memory, and interconnection blocks. The proposed many-core architecture is built using multiple processing clusters coupled with a NoC for communication which allows a high degree of design scalability. The processing cluster inside features a configurable multi-core architecture consisting of multiple RISC-V processing elements (PE) tightly coupled with a bus-based interconnection for intra-cluster communication using parameterized scratchpad shared memory. Each PE features a single RISC-V core with a tightly coupled parameterized scratchpad local memory and generic AXI interface. Evaluation results demonstrate that the proposed architecture features a scalable computing performance of 501 MOp/s for 4 clusters and 878 MOp/s for 8 clusters. Moreover, a scalable memory bandwidth up to 4.3 GB/s is achieved for 9 clusters with a power consumption of 1.4 W per cluster utilizing 7.7% of on-chip memory resources. The many-core architecture is implemented and evaluated on Xilinx Virtex Ultrascale+ with the feature of changing the architecture configurations during run-time using dynamic and partial reconfiguration which provides more flexibility and re-usability.

Programmable logic devices – key components for today’s and tomorrow’s electronic-based systems

Since their introduction in the 1970s, Programmable Logic Devices (PLDs) evolved from implementing small glue-logic designs to large, configurable multi-processor Systems-on-Chip (SoC). Today’s most prominent PLD technology, known as FPGA (Field-Programmable Gate Array), is used in an increasing number of application domains, such as the telecom industry, the automotive electronics sector or automation technology, and recent market studies expect a continuous demand for these sophisticated microelectronic devices in the future. For small and medium enterprises and/or SME-dominated countries like Austria, FPGAs can provide access to VLSI (Very Large Scale Integration) technology by avoiding the immense NRE (Non-Recurring Engineering) costs of ASICs (Application-Specific Integrated Circuits). This work outlines how today’s and future electronic-based systems can benefit from FPGA technology. Trends, tools and design flows will be explained as well as research challenges that are currently investigated within two public funded R&D projects at the University of Applied Sciences Technikum Wien.

Recycled FPGA Detection Using Exhaustive LUT Path Delay Characterization and Voltage Scaling

Field-programmable gate arrays (FPGAs) have been extensively used because of their lower nonrecurring engineering and design costs, instant availability and reduced visibility of failure, high performance, and power benefits. Reports indicate that previously used or recycled FPGAs are infiltrating the electronics’ supply chain and making the security and reliability of the critical systems and networks vulnerable. Current recycled integrated circuit (IC) detection procedures include parametric, functional, and burn-in tests that require golden or reference data. Besides, they are time consuming, require expensive equipment, and do not focus on FPGAs. In this article, we propose two recycled FPGA detection methods based on supervised and unsupervised machine learning algorithms. We develop a sophisticated ring oscillator (RO) design to exploit the degradation of lookup tables (LUTs) and use them in the proposed methods. In the supervised method, a one-class classifier is trained with RO frequencies, kurtosis, and skewness data obtained from unused FPGAs, which differentiates unused and aged FPGAs. The unsupervised method uses $k$ -means clustering and Silhouette value analysis to detect suspect recycled components with very little (if any) golden information. In addition, we introduce a voltage scaling-assisted RO frequency measurement technique that improves the classification. The proposed methods are examined for Spartan-3A and Spartan-6 FPGAs, and the result shows that both methods are effective in detecting recycled FPGAs, which experience accelerated aging for at least 12 h equivalent to 70 days in real-time age.

Integration and Verification Approach of ISTSat-1 CubeSat

Large-scale space projects rely on a thorough Assembly, Integration, and Verification (AIV) process to provide the upmost reliability to spacecraft. While this has not traditionally been the case with CubeSats, their increasing role in space science and technology has led to new verification approaches, including in educational CubeSats. This work describes the integration and verification approach for ISTSat-1, which is an educational CubeSat from the Instituto Superior Técnico in Portugal that partially discards the typical stage-gate approach to spacecraft development in favor of a more iterative approach, allowing for the system-level verification of unfinished prototypes. Early verification included software functional testing on a flatsat model, thermal vacuum and vibration testing on a battery model, ionizing radiation testing on the on-board computer, and non-ionizing radiation (EMC) testing on all subsystems. The testing of functional prototypes at an early development stage led to uncovering system-level errors that would typically require hardware redesign at a later project stage. The team considers the approach to be useful for educational projects that employ a small, co-located team with low non-recurring engineering costs.

Logic IP for Low-Cost IC Design in Advanced CMOS Nodes

Routing closure and design-for-manufacturability (DFM) challenges exacerbate nonrecurring engineering (NRE) costs, a steep barrier to entry for advanced sub-20-nm CMOS nodes, making low-volume fabrication of integrated circuits (ICs) almost intangible. For ICs in which the cost of design dominates the fabrication, we seek to trade some amount of chip area to lower NRE costs. To this end, we consider designing logic cell layouts for easier routing and DFM closure. We accustom a layout simplification and reuse approach to build standard cell libraries such that good pin access and layout regularity are ensured for all cells. Using a commercial 14-/16-nm technology, we developed two 100-cell logic cell libraries that are, respectively, 9 and 10.5 metal tracks tall. Our routing experiments on multiple designs show that taller cells can endure 20% higher placement density while reducing the number of design rule check (DRC) violations by four orders of magnitude compared with a commercial 7.5 track library. Silicon measurements show that taller cells can enable faster design closure in ICs with stringent performance requirements at the cost of a marginal power overhead. Finally, our logic cell design approach can make advanced CMOS nodes more affordable for low-volume design.

Novel ASIC Design Flow Using Dynamic Libraries for Reducing Design Time

This paper presents an Electronic Design Automation (EDA) methodology, capable of complete ASIC design flow. It reduces the Non-Recurring Engineering (NRE) Cost by introducing a novel concept of dynamic technology library (DTL), which stores the layout and physical design information of each block in a design. DTLs are dynamically updated with a verified physical block, whenever a new design (not available in DTL) is synthesized. The key feature of DTL is that it offers reusability of verified physical blocks at different levels of abstraction (registers, functional units, gates etc.) thereby reducing the NRE cost. A depth based search technique is employed that allows partial or full reuse of pre-compiled and optimized design layouts. The proposed tool flow is validated using 16 designs from IWLS2005 benchmark suite, including one 32-bit ALU and a 15 tap FIR filter (widely used as a signal processing element). It is shown that the reusability offered by DTL makes it possible to reduce the design time by more than 90% in comparison to other EDA methodologies.

FPGA-based design of advanced BMS implementing SoC/SoH estimators

Energy storage system, usually a battery, become essential part for all electric drive vehicles such as hybrid electric vehicle (HEV), plug-in hybrid electric vehicle (PHEV) and electric vehicle (EV) in the coming decades. These energy storage systems include Li-ion batteries, Ni-MH batteries, lead-acid batteries and ultra-capacitors. An accurate Battery Management System (BMS) is highly demanded integrated system in all electric derive vehicles to ensure the optimum use of an energy storage system. The battery's state monitoring & evaluation, charge control and cell balancing are the important features of any BMS. However, due to unavailability of inaccurate battery's state-of-charge (SoC)/state-of-health (SoH) estimators and uncertainty of battery's performance, new approaches of BMS design are under development to control batteries optimally and hence, the vehicle performance. In addition, most of the existing BMSs either do not provide SoH at all or provide it as a function of capacity degradation over the battery usage. This research paper presents the field-programmable gate array (FPGA) - based Advanced BMS design using MATLAB-to-FPGA design flow. The Advanced BMS design provides the combined estimation of both SoC and SoH of a rechargeable battery. This research paper also summarizes the Neuro-Fuzzy & statistical models implemented in Advanced BMS for accurate estimation of battery's SoC & SoH respectively. Further, this research paper presents the selection of suitable FPGA and its hardware realization implementing Advanced BMS. Finally, the experimental results are confirmed by simulation and synthesis of its register transfer level (RTL) design. FPGA-based Advanced BMS would provide the best chip solution for a generalized BMS with benefits of low Non-recurring engineering (NRE) cost, low power consumption, high speed of operation, large reconfigurable logic and large data storage capacity.

Power efficient optimum design of the Reversible Plessey Logic Block of a field-programmable gate array

Reversible logic has captured significant attention in recent time for its reduced power consumption property which is one of the main concerns of digital logic design. Reprogram ability, higher speed, higher density, non-recurring engineering (NRE) costs, massive parallel operations and many other favoring factors have made prominent use of the Field-Programmable Gate Array (FPGA) in today's electronics world. In this paper, the most significant part of an FPGA, the Plessey Logic Block is designed in reversible manner with optimal parameters. On the way to design the proposed reversible Plessey Logic Block, each individual components such as reversible D-Latch, reversible Decoder, reversible Multiplexer, reversible Master-Slave Flip-Flop, reversible RAM are designed separately.. The proposed design of the individual parts is primarily optimized for the number of gates, garbage outputs, quantum cost and delay. In addition, area and power are optimized to ensure the power efficiency of the circuits. Two 4×4 reversible gates, namely HNF (Hafiz-Naz-Flip-Flop) gate and HND (Hafiz-Naz-Decoder) gate, are proposed to achieve the optimization goal. Moreover, proposed algorithms, lemmas and theorems certify the novelty of the proposed design. Compared to previous works, the proposed counter parts of Reversible Plessey Logic Block require less number of gates, garbage outputs, quantum cost and the delay. Finally, the proposed Reversible Plessey (4×2) Logic Block is compared with existing designs. The comparative result proves the efficacy and novelty of the proposed design showing improvement 51.62% in terms of number of transistor, 73.57% in terms of area (mm2) and 34.12% in terms of power (mW) with respect to the corresponding metrics of the best design in literature.

Moonwalk

Cloud services are becoming increasingly globalized and data-center workloads are expanding exponentially. GPU and FPGA-based clouds have illustrated improvements in power and performance by accelerating compute-intensive workloads. ASIC-based clouds are a promising way to optimize the Total Cost of Ownership (TCO) of a given datacenter computation (e.g. YouTube transcoding) by reducing both energy consumption and marginal computation cost. The feasibility of an ASIC Cloud for a particular application is directly gated by the ability to manage the Non-Recurring Engineering (NRE) costs of designing and fabricating the ASIC, so that it is significantly lower (e.g. 2X) than the TCO of the best available alternative. In this paper, we show that technology node selection is a major tool for managing ASIC Cloud NRE, and allows the designer to trade off an accelerator's excess energy efficiency and cost performance for lower total cost. We explore NRE and cross-technology optimization of ASIC Clouds for four different applications: Bitcoin mining, YouTube-style video transcoding, Litecoin, and Deep Learning. We address these challenges and show large reductions in the NRE, potentially enabling ASIC Clouds to address a wider variety of datacenter workloads. Our results suggest that advanced nodes like 16nm will lead to sub-optimal TCO for many workloads, and that use of older nodes like 65nm can enable a greater diversity of ASIC Clouds.

Moonwalk

Cloud services are becoming increasingly globalized and data-center workloads are expanding exponentially. GPU and FPGA-based clouds have illustrated improvements in power and performance by accelerating compute-intensive workloads. ASIC-based clouds are a promising way to optimize the Total Cost of Ownership (TCO) of a given datacenter computation (e.g. YouTube transcoding) by reducing both energy consumption and marginal computation cost. The feasibility of an ASIC Cloud for a particular application is directly gated by the ability to manage the Non-Recurring Engineering (NRE) costs of designing and fabricating the ASIC, so that it is significantly lower (e.g. 2X) than the TCO of the best available alternative. In this paper, we show that technology node selection is a major tool for managing ASIC Cloud NRE, and allows the designer to trade off an accelerator's excess energy efficiency and cost performance for lower total cost. We explore NRE and cross-technology optimization of ASIC Clouds for four different applications: Bitcoin mining, YouTube-style video transcoding, Litecoin, and Deep Learning. We address these challenges and show large reductions in the NRE, potentially enabling ASIC Clouds to address a wider variety of datacenter workloads. Our results suggest that advanced nodes like 16nm will lead to sub-optimal TCO for many workloads, and that use of older nodes like 65nm can enable a greater diversity of ASIC Clouds.

Specializing a Planet's Computation: ASIC Clouds

GPU- and FPGA-based clouds have been deployed to accelerate computationally intensive workloads. ASIC-based clouds are a natural evolution as cloud services expand across the planet. ASIC Clouds are purpose-built datacenters comprising large arrays of ASIC accelerators that optimize the total cost of ownership (TCO) of large, high-volume scale-out computations. On the surface, ASIC Clouds may seem improbable due to high nonrecurring engineering (NRE) costs and ASIC inflexibility, but large-scale ASIC Clouds have been deployed for the Bitcoin cryptocurrency system. This article distills lessons from these Bitcoin ASIC Clouds and applies them to other large-scale workloads, including YouTube-style video-transcoding and Deep Learning, showing superior TCO versus CPU and GPU. It derives Pareto-optimal ASIC Cloud servers based on accelerator properties, by jointly optimizing ASIC architecture, DRAM, motherboard, power delivery, cooling, and operating voltage. Finally, the authors examine the impact of ASIC NRE and when it makes sense to build an ASIC Cloud.