Logic IP for Low-Cost IC Design in Advanced CMOS Nodes

Abstract

Routing closure and design-for-manufacturability (DFM) challenges exacerbate nonrecurring engineering (NRE) costs, a steep barrier to entry for advanced sub-20-nm CMOS nodes, making low-volume fabrication of integrated circuits (ICs) almost intangible. For ICs in which the cost of design dominates the fabrication, we seek to trade some amount of chip area to lower NRE costs. To this end, we consider designing logic cell layouts for easier routing and DFM closure. We accustom a layout simplification and reuse approach to build standard cell libraries such that good pin access and layout regularity are ensured for all cells. Using a commercial 14-/16-nm technology, we developed two 100-cell logic cell libraries that are, respectively, 9 and 10.5 metal tracks tall. Our routing experiments on multiple designs show that taller cells can endure 20% higher placement density while reducing the number of design rule check (DRC) violations by four orders of magnitude compared with a commercial 7.5 track library. Silicon measurements show that taller cells can enable faster design closure in ICs with stringent performance requirements at the cost of a marginal power overhead. Finally, our logic cell design approach can make advanced CMOS nodes more affordable for low-volume design.