Enabling Design of Low-Volume High-Performance ICs

Abstract

Integrated circuits (ICs) are ubiquitous, ranging from consumer electronics to custom hardware. While scaling of CMOS feature sizes has enabled faster and smaller ICs, manufacturing smaller transistors and wires has become more challenging, particularly with the sub-wavelength lithography era. In response, foundries, to ensure the manufacturability of ICs at advanced CMOS nodes, have increased the number of design rules. The resultant difficulty in achieving design closure threatens the ability to create custom ICs within required timeframes. As a result, the use of advanced CMOS nodes has become unfavorable particularly for low-volume ICs wherein the design cost is higher than the fabrication cost. To this end, this dissertation explores opportunities to extend the use of advanced CMOS nodes for low-volume ICs by trading some amount of chip area for a reduction in design complexity, but without significantly affecting the performance and power consumption of ICs. To pursue this objective, we propose finding more optimal logic cell heights and wire pitches by selecting values more relaxed than the technology-allowed minimums.To evaluate the impact of this optimization, we designed multiple digital ICs in a commercial 14/16 nm FinFET process. The silicon measurements indicate that relaxing the wiring pitches can reduce power consumption through coupling capacitance reduction. Moreover, taller logic cells that pose a minimal area increase penalty still perform comparably to shorter logic cells while eliminating routing problems. Lastly, using a layout pattern enumerator developed in-house, cell height increase is shown to mitigate manufacturing risks via layout simplification and re-use. These results suggest that logic cell height and wire pitch optimizations provide an excellent foundation for enabling low-volume customers to fabricate ICs in advanced CMOS nodes.