CMOS gate dielectric scaling was one of the key technology options for boosting the device performance and for keeping the device downsizing on track up to the recent technology nodes. The conventional homopolar dielectric films such as silicon oxide or silicon nitride were used and scaled down to about 1 nm which was well below the direct tunneling limit of 3 nm thick and the gate oxide thickness was the first key device parameter being shrunk into the nanometer scale. However, the physical limit, the exponentially increase in the gate leakage current, and the poor film uniformity control of ultrathin oxide had inhibited the further downscaling of this kind gate dielectric film. High dielectric constant (HiK) heteropolar metal oxides such as Hf-based or La-based dielectric materials, with several nanometers thick, are able to achieve a capacitance value that is equivalent to a silicon oxide (known as Equivalent Oxide Thickness, or EOT) with thickness in the nanometer or even subnanometer scale and with a gate leakage current of several orders of magnitude smaller. The use of EOT makes the gate dielectric scaling beyond the atomic scale be possible. However, just a couple generations since Intel introduced Hf-based HiK in the 45 nm technology processor production, HiK scaling has already lost its momentum. The last ITRS roadmap for EOT scaling was 0.03 nm reduction per generation and the EOT used the latest fabrication processes was still thicker than 0.7 nm which is the physical limit of bulk silicon oxide. For HiK scaling down to half nanometer EOT range, we shall encounter most of the nonscalabilities as found in the ultrathin silicon oxide film and the challenges is now even tougher. The surface roughness and the interface layer are not only non-scalable, they impose the lower bound for smallest achievable EOT for maintaining device scaling. HiK metal oxides have much poorer properties and less thermally stable when they interface with the silicon substrate and gate electrode. Depending on the processing temperature, partial pressure of oxygen, several different chemical reactions may take place at the interfaces and even in the bulk of HiK layer. The thermally-induced interfacial silicate layer is rougher than the native oxide prepared by atomic-layer deposition and it leads to the significant increase in EOT. The gate electrode layer on the HiK layer has even larger roughness than HiK and will lead to both EOT and electrical characteristic degradation. The thickness variations result in both gate capacitance and local electrostatic field fluctuation which are insignificant with the present fabrication processes when the film is not too thin and the device size is not too small; they will become significant in the nanoscale devices. In addition, Fowler-Norheim and direct tunneling current of HiK films will occur at a much thicker physical thickness as HiK materials usually have much smaller band offsets with silicon and sometimes have heavier carrier effective masses. In principle, a half nanometer EOT gate dielectric film might be achieved with a 3.5 nm thick La2O3 film. At this thickness, direct tunneling should occur and it is expected that the La2O3 film should have a large gate leakage current not to mention the further conduction enhancement due to oxide traps. HiK materials are often found to have much higher bulk traps than the silicon oxide because of the presents of oxygen vacancies and grain boundary states of nanocrystalline phases of metal oxides. These non-ideal factors have been the major constraints for further EOT scaling in the half nanometer range. There are no much options for getting rid of these technology issues. Better uniformity control and low thermal budget process can help to alleviate some of the aforementioned issues. Regarding the alternate HiK candidates, comprehensive studies had been conducted on almost every elemental dielectric materials. The most favorable and yet feasible candidates are still limited to HfO2 and La2O3 and unfortunately they are not good enough in the half nanometer EOT range. Multilayer stack is not likely be a feasible option from the EOT point of view. Yet the only possible option is the use of complex oxides. We shall discuss some recent achievements and the future perspectives on these issues.
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Jan 1, 2018
Yue Sun + 2
Open Access