Non-binary LDPC Codes Research Articles

New Stopping Criterion for Fast Low-Density Parity-Check Decoders

Low-density parity-check (LDPC) codes are favorable in low bit-error-rate and high code-rate applications. However, the decoding complexity for LDPC codes is quite large, especially for nonbinary LDPC codes. In this paper, we propose a new T-tolerance stopping criterion for LDPC decoders by exploiting the fact that the total aposteriori probability (APP) should increase across iterations when message passing (MP) algorithms are employed. Simulation results demonstrate that our proposed new T-tolerance criterion can greatly reduce the average iteration number (complexity) while the decoding performance degradation is controlled within 0.1 dB in the low bit-energy-to-noise-spectral-density ratio (Eb/N0) scenarios.

Generalized Binary Representation for the Nonbinary LDPC Code With Decoder Design

In this paper, we consider the performance-optimized nonbinary low-density parity check code over general linear group, i.e., <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="TeX">$\bar{\cal C}$</tex-math></inline-formula> . A new methodology for constructing the binary representation [generalized binary representation (GBR)] of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="TeX">$\bar{\cal C}$</tex-math></inline-formula> is proposed, which can be optimized with regard to both degree distributions and girth. As to the decoding of the GBR, we develop a low-complexity hybrid parallel decoding process. It is shown that the decoding performance of the GBR under the proposed binary decoding process could closely approach the decoding performance of its mother code <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="TeX">$\bar{\cal C}$</tex-math></inline-formula> under nonbinary belief propagation decoding. A simple code optimization algorithm for the GBR is also provided. Simulations show the comparative results and justify the advantages of the proposed constructions.

GPU Accelerated Belief Propagation Decoding of Non-Binary LDPC Codes with Parallel and Sequential Scheduling

Low-Density Parity-Check (LDPC) codes are very powerful channel coding schemes with a broad range of applications. The existence of low complexity (i.e., linear time) iterative message passing decoders with close to optimum error correction performance is one of the main strengths of LDPC codes. It has been shown that the performance of these decoders can be further enhanced if the LDPC codes are extended to higher order Galois fields, yielding so called non-binary LDPC codes. However, this performance gain comes at the cost of rapidly increasing decoding complexity. To deal with this increased complexity, we present an efficient implementation of a signed-log domain FFT decoder for non-binary irregular LDPC codes which exploits the inherent massive parallelization capabilities of message passing decoders. We employ Nvidia's Compute Unified Device Architecture (CUDA) to incorporate the available processing power of state-of-the-art Graphics Processing Units (GPUs). Furthermore, we present a CUDA implementation of the signed-log domain FFT decoder using the so-called layered update rule, in which check nodes are updated one after another. This sequential updating of nodes has been shown to converge about twice as fast as the traditional flooding scheme. To achieve a high speedup of the layered CUDA implementation, we employ quasi-cyclic non-binary LDPC codes since they allow to update multiple neighboring check nodes in parallel without any performance loss.

Non-Binary Protograph-Based LDPC Codes: Enumerators, Analysis, and Designs

This paper provides a comprehensive analysis of nonbinary low-density parity check (LDPC) codes built out of protographs. We consider both random and constrained edge-weight labeling, and refer to the former as the unconstrained nonbinary protograph-based LDPC codes (U-NBPB codes) and to the latter as the constrained nonbinary protograph-based LDPC codes (C-NBPB codes). Equipped with combinatorial definitions extended to the nonbinary domain, ensemble enumerators of codewords, trapping sets, stopping sets, and pseudocodewords are calculated. The exact enumerators are presented in the finite-length regime, and the corresponding growth rates are calculated in the asymptotic regime. An EXIT chart tool for computing the iterative decoding thresholds of protograph-based LDPC codes is presented, followed by several examples of finite-length U-NBPB and C-NBPB codes with high performance. Throughout this paper, we provide accompanying examples, which demonstrate the advantage of nonbinary protograph-based LDPC codes over their binary counterparts and over random constructions. The results presented in this paper advance the analytical toolbox of nonbinary graph-based codes.

Joint detection – decoding of majority‐logic decodable non‐binary low‐density parity‐check coded modulation systems: an iterative noise reduction algorithm

In this study, the authors present a low-complexity iterative joint detection–decoding algorithm for majority-logic decodable non-binary low-density parity-check (LDPC) coded modulation systems. In the proposed algorithm, a hard-in–hard-out decoder is combined with a hard-decision signal detector in an iterative manner. Each iteration consists of five phases. Firstly, the detector makes hard decisions based on the iteratively updated ‘received’ signals; secondly, these hard decisions are distributed via variable nodes to check nodes; thirdly, check nodes compute hard extrinsic messages; fourthly, each variable node counts hard extrinsic messages from its adjacent check nodes and feeds back to the detection node the symbol with the most votes as well as the difference between the most votes and the second most votes; finally, these feedbacks are used to shift each ‘received’ signal point along an estimated direction to possibly reduce noise. The proposed algorithm requires only integer operations and finite field operations and consequently can be implemented with simple combinational logic circuits in practical systems. Simulation results show that the proposed algorithm performs well and hence serves as an attractive candidate for trading off performance against complexity for majority-logic decodable non-binary LDPC codes.

An Improved Construction for Yielding Nonbinary LDPC Codes

In this paper, we investigate construction methods for producing nonbinary LDPC codes, and a family of nonbinary LDPC codes over is presented and its properties are derived. Compared to the second method presented by Ref. [5], simulation results show that the proposed LDPC codes perform well over the AWGN channel under belief propagation decoding algorithm and have an almost same BER curve as the ones in Ref. [5]. However, the resultant construction method is simpler than the latter’s.

Non-Binary LDPC Decoder Based on Symbol Flipping with Multiple Votes

In this letter, a new algorithm to decode non-binary LDPC (NB-LDPC) codes is proposed. This algorithm is inspired from very low complexity decoders that have been proposed recently, in which only syndrome computations at the check node update are used, while performing symbol-flipping based update at the variable node. Usually, the low complexity decoders based on symbol flipping suffer from a non-negligible performance degradation compared to soft-decision NB-LDPC decoders. Our improved decoder makes use of a list of syndrome computations instead of a single one based on hard-decision, and builds soft information at the variable node input by assigning votes weighted by different amplitudes. Simulations show that using multiple votes with multiple weights yields better performance, while still maintaining the low complexity feature.

Structured Bit-Interleaved LDPC Codes for MLC Flash Memory

Due to a structural feature in the programming process of MLC (two bits per cell) and TLC (three bits per cell) flash memory, the majority of errors that occur are single-bit errors. Moreover, the voltages used to store the bits typically result in different bit error probabilities for the two or three types of bits. In this work we analyze binary regular LDPC codes in the standard bit-interleaved coded modulation implementation, assuming different probabilities on the bits, to determine what ratio of each type of bit should be connected at the check nodes to improve the decoding threshold. We then propose a construction of nonbinary LDPC codes using their binary images, resulting in check node types that come close to these optimal ratios.

Finite Field Spreading for Multiple-Access Channel

As a generalization of the binary spreading scheme in conventional direct-sequence code-division multiple-access (DS-CDMA) and interleave-division multiple-access (IDMA), a finite field spreading scheme is proposed for a synchronous multiple-access channel (MAC) with Gaussian noise and equal-power users. For each user, each information symbol over a finite field is spread into a length-L field vector by L-field multiplications. At the receiver, an iterative multi-user decoding algorithm on a factor graph is developed to recover each user's information symbol. To estimate the bit error rate performance of an uncoded finite field spreading system, an extrinsic information transfer analysis of the finite field despreading is given. This analysis shows that in addition to overcoming multi-user interference, the finite field spreading scheme can also provide an additional coding gain to overcome Gaussian noise compared with the conventional spreading scheme. This coding gain increases with the field order. The finite field spreading serially concatenated with a nonbinary low-density parity-check (LDPC) code, with field order 64, approaches the MAC capacity within 0.26 dB at a sum rate of 0.25.

A Decoding Algorithm Based on Layered Decoding and Min-max for Nonbinary LDPC Codes

摘要: 该文在现有译码算法的基础上提出一种高效的非二进制低密度奇偶校验码(NB-LDPC)译码方法，充分利用了分层译码算法与Min-max算法的优点，不但译码复杂度低、需要的存储空间小，而且可将译码速度提高一倍。应用该算法，对一种定义在GF(25)上的(620,509)码进行了仿真。该码的仿真结果表明：在相同误码率下，该文译码算法所需最大迭代次数仅为Zhang的算法(2011)的45%。 关键词: 非二进制低密度奇偶校验码(NB-LDPC) / 分层译码 / Min-max / 准循环码

Design of efficiently encodable nonbinary LDPC codes for adaptive coded modulation

This paper is concerned with constructions of nonbinary low-density parity-check (LDPC) codes for adaptive coded modulations (ACM). A new class of efficiently encodable structured nonbinary LDPC codes are proposed. The defining parity-check matrices are composed of scalar circulant sub-matrices which greatly reduce the storage requirement when compared with random LDPC codes. With this special structure of parity-check matrix, an efficient encoding algorithm is presented. Based on the proposed codes, a family of variablerate/variable-field nonbinary LDPC codes is designed for the ACM system. When combined with matched-size signal constellations, the family of constructed codes can achieve a wide range of spectral efficiency. Furthermore, the resultant ACM system can be implemented via a set of encoder and decoder. Simulation results show that the proposed nonbinary LDPC codes for the ACM system perform well.

Research of FH-MFSK Underwater Acoustic Communication Based on Non-Binary LDPC Codes

Compared with binary-modulation, Multiple-modulation can obtain higher rate of transmission in the condition of same symbol-rate. If using binary channel codes with multiple-modulation, there exists an problem of information-loss of the probability from bit to symbol conversion. Underwater acoustic channel is an multipath, time-variation, high-noise and strong doppler-effect wireless channel, which leads to high error-rate caused by signal distortion. To solve the problems above, we adopt FH-MFSK modulation to overcome the inter-symbol interference by multipath. The PN sequence is used as a frame synchronization signal and frequency energy accumulation method is used to detect the frame-synchronization. PN hopping signal is chosen to estimate the doppler frequency-shift and using non-binary LDPC codes based on symbol for channel error codes. Finally, We perform numerical simulations and the experiments on the lake to show that compared with binary LDPC codes, non-binary LDPC codes for multiple-modulation can achieve same error-rate under lower SNR.

Research of FH-MFSK Underwater Acoustic Communication Based on Non-Binary LDPC Codes

Compared with binary-modulation, Multiple-modulation can obtain higher rate of transmission in the condition of same symbol-rate. If using binary channel codes with multiple-modulation, there exists an problem of information-loss of the probability from bit to symbol conversion. Underwater acoustic channel is an multipath, time-variation, high-noise and strong doppler-effect wireless channel, which leads to high error-rate caused by signal distortion. To solve the problems above, we adopt FH-MFSK modulation to overcome the inter-symbol interference by multipath. The PN sequence is used as a frame synchronization signal and frequency energy accumulation method is used to detect the frame-synchronization. PN hopping signal is chosen to estimate the doppler frequency-shift and using non-binary LDPC codes based on symbol for channel error codes. Finally, We perform numerical simulations and the experiments on the lake to show that compared with binary LDPC codes, non-binary LDPC codes for multiple-modulation can achieve same error-rate under lower SNR.

Serial Min-max Decoding Algorithm Based on Variable Weighting for Nonbinary LDPC Codes

In this paper, we perform an analysis on the min-max decoding algorithm for nonbinary LDPC(low-density parity-check) codes and propose serial min-max decoding algorithm. Combining with the weighted processing of the variable node message, we propose serial min-max decoding algorithm based on variable weighting for nonbinary LDPC codes in the end. The simulation indicates that when the bit error rate is 10^-3,compared with serial min-max decoding algorithm ,traditional min-max decoding algorithm and traditional minsum algorithm ,serial min-max decoding algorithm based on variable weighting can offer additional coding gain 0.2dB、0.8dB and 1.4dB respectively in additional white Gaussian noise channel and under binary phase shift keying modulation. DOI : http://dx.doi.org/10.11591/telkomnika.v12i2.4176

The Min-max Decoding Algorithm of Nonbinary

In this paper, we propose the min-max decoding algorithm of nonbinary LDPC codes based on early stopping by analyzing and combining traditional min-max decoding algorithm of nonbinary LDPC codes and the early stopping rule of binary LDPC codes. The simulation indicates that the proposed algorithm can greatly reduce the number of iterations in decoding process with almost no decoding performance loss compared with traditional minsum decoding algorithm of nonbinary LDPC codes and traditional min-max decoding algorithm of nonbinary LDPC codes in low signal-to-noise ratio region , which is in additive Gaussian white noise channel and under binary phase shift keying modulation. So the computational complexity can be effectively reduced and the real-time performance can be well improved.

Dynamic Check Message Majority-Logic Decoding Algorithm for Non-binary LDPC Codes

Majority-logic algorithms are devised for decoding non-binary LDPC codes in order to reduce computational complexity. However, compared with conventional belief propagation algorithms, majority-logic algorithms suffer from severe bit error performance degradation. This paper presents a low-complexity reliability-based algorithm aiming at improving error correcting ability of majority-logic algorithms. Reliability measures for check nodes are novelly introduced to realize mutual update between variable message and check message, and hence more efficient reliability propagation can be achieved, similar to belief-propagation algorithm. Simulation results on NB-LDPC codes with different characteristics demonstrate that our algorithm can reduce the bit error ratio by more than one order of magnitude and the coding gain enhancement over ISRB-MLGD can reach 0.2-2.0dB, compared with both the ISRB-MLGD and IISRB-MLGD algorithms. Moreover, simulations on typical LDPC codes show that the computational complexity of the proposed algorithm is closely equivalent to ISRB-MLGD algorithm, and is less than 10% of Min-max algorithm. As a result, the proposed algorithm achieves a more efficient trade-off between decoding computational complexity and error performance.

Message Passing Decoder with Decoding on Zigzag Cycles for Non-binary LDPC Codes

Message Passing Decoder with Decoding on Zigzag Cycles for Non-binary LDPC Codes

Density Evolution for the Design of Non-Binary Low Density Parity Check Codes for Slepian-Wolf Coding

In this paper, we investigate the problem of designing good non-binary LDPC codes for Slepian-Wolf coding. The design method is based on Density Evolution which gives the asymptotic error probability of the decoder for given code degree distributions. Density Evolution was originally introduced for channel coding under the assumption that the channel is symmetric. In Slepian-Wolf coding, the correlation channel is not necessarily symmetric and the source distribution has to be taken into account. In this paper, we express the non-binary Density Evolution recursion for Slepian-Wolf coding. From Density Evolution, we then perform code degree distribution optimization using an optimization algorithm called differential evolution. Both asymptotic performance evaluation and finite-length simulations show the gain at considering optimized degree distributions for SW coding.

English

English

Efficient Check Node Processing Architectures for Non-binary LDPC Decoding Using Power Representation

When the code length is moderate, non-binary low-density parity-check (NB-LDPC) codes can achieve better error correcting performance than their binary counterparts at the expense of higher decoding complexity. The check node processing is a major bottleneck of NB-LDPC decoding. This paper proposes a novel scheme for the forward-backward check node processing by making use of the cyclical-shift property of the power representation of finite field elements. Compared to previous designs, the proposed check node units (CNUs) do not need the complex switching network. Moreover, the multiplications of the parity check matrix entries are efficiently incorporated. For a Min-max NB-LDPC decoder over GF(32), the proposed schemes reduce the CNU area by at least 32%, and lead to higher clock frequency than prior efforts.