Non-binary LDPC Codes Research Articles

Low Complexity Bit Reliability and Predication Based Symbol Value Selection Decoding Algorithms for Non-Binary LDPC Codes

The main challenge for hardware implementation of non-binary LDPC decoding is the high computational complexity and large memory requirement. To address this challenge, five new low complexity LDPC decoding algorithms are proposed in this paper. The proposed algorithms are developed specifically towards the low complexity, yet effective, decoding of the NB LDPC codes. The proposed decoding algorithms update, iteratively, the hard decision received vector to search for the valid codeword in the vector space of Galois field ${(GF)}$ . The selection criterion for least reliable symbol positions is based on the information from the failed checks and the reliability information from the Galois field structure as well as from the received channel soft information. To choose the correct value for the candidate symbol, two methods are used. The first method is based on the prediction of the error symbol from the set of Galois field symbols which maximize an objective function. In the second method, individual bits are flipped based on the reliability information obtained from the channel. Algorithms 1 and 2 flip a single symbol per iteration whilst the other three algorithms 3 , 4 and 5 flip multiple symbols in each iteration. The proposed voting based Algorithms 1 , 2 and 5 first short list the unreliable positions using a majority voting scheme and then choose the candidate symbol value from the set of the symbols in ${GF(q)}$ while not violating the field order ${q}$ . These methods simplify the decoding complexity in terms of computation and memory. Results and analysis of these algorithms show an appealing tradeoff between computational complexity and bit error rate performance for NB LDPC codes.

A Unified Multiuser Coding Framework for Multiple-Access Technologies

In this paper, multiple-access techniques are viewed as generalized coding schemes to support both multiuser separation and coding gain. In this sense, the traditional coding schemes, e.g., low-density parity-check (LDPC) code, can be viewed as a special case. Note that still a big difference exists between multiple-access techniques and LDPC codes. In particular, both binary and nonbinary LDPC codes are generated based on finite field theory, whereas multiple-access works based on not necessarily a finite field. This paper presents a mathematical framework, called “multiuser coding,” to unify multiple-access and traditional coding theories. To verify the proposed framework, we propose a uniquely decodable mapping based codebook for futuristic multiple-access communications. A three-dimensional Tanner graph based message passing algorithm is introduced for multiuser detection. Simulation results show that the proposed scheme can support a large number of users with a promising performance.

Combination of High-Order Modulation and Non-Binary LDPC Codes over GF(7) for Non-Linear Satellite Channels

High-order modulations are necessary to improve the bandwidth efficiency of the satellite communication system. However, the non-linear characteristic of satellite channels limits the application of high-order modulations. In this paper, we propose a new 7-point constellation which is expected to be effectively applied to the satellite communication system, and combine it with non-binary low-density parity-check (NB-LDPC) codes over Galois field GF(7) to guarantee the reliability of the data transmission. The exact expression for the average symbol error probability (SEP) of 7-order quadrature amplitude modulation (7-QAM) over the Additive White Gaussian Noise (AWGN) channel is derived, and the non-linear distortion over satellite channels is also analyzed. Simulation results reveal that, compared with the traditional 8-order phase-shift keying (8-PSK), the 7-QAM method can achieve about 3 dB gain over the AWGN channel without channel coding at symbol error rate (SER) of 10 - 6 . Moreover, the proposed combined coded modulation scheme also has better SER performance than the NB-LDPC coded 8-PSK modulation scheme over the non-linear satellite channel.

High-Efficient Adaptive Modulation for PWM-Based Multi-Level Perpendicular Magnetic Recording on Insufficient Resolution Channel

In this paper, we propose a high-efficient constrained adaptive 5-binary to 4-ternary (5B4T)-modulation in pulsewidth modulation (PWM)-based ternary perpendicular magnetic recording (PMR). The high-efficient modulation is required to obtain higher user-bit density (UBD) gain in low-resolution channel, in which transition interval and magnetic-grain size are equivalent on media. In our proposed constrained adaptive 5B4T-modulation, one mapping-set is adaptively selected from the prepared two different mapping-sets to satisfy a specific constraint of ternary signal in modulation block-by-block. For the signal detection in the proposed modulation, we provide a practical solution which is a blind-detection method on likelihood vector. The likelihood vector is re-calculated as joint-metric using the likelihood values of adjacent modulation blocks. By using the vector of joint-metric, a likelihood vector is further generated to decode non-binary low-density parity-check (NB-LDPC) codes. Our simulation results demonstrate that the proposed adaptive 5B4T-modulated PWM-based ternary-PMR, combined with NB-LDPC codes over GF(32), shows a significant robustness in ultra-low-resolution channel, which occurs magnetization-missing frequently.

Pergroup and Joint Optimization of Max-Dmin Precoder for MIMO with LDPC Coding Using QAM Modulation

MIMO technology not only offers diversity and capacity gains, but also provides higher spectral efficiency and significant link reliability over SISO systems. Many methods are developed to exploit the diversity offered by multi-antenna systems such as Alamouti code and spatial multiplexing that do not require transmitter-side channel status information (Tx-CSI). Other power allocation optimization techniques, also known as precoding, require a full or partial Tx-CSI. These techniques aim to transform the signal before transmission according to different criteria, among which the minimal Euclidean distance seems to be very effective and continues to interest the researchers. Given perfect channel state information at both sides of the communication, we propose in this paper a novel design of wireless transmission schemes that joint the minimal Euclidean distance precoder and error correction coding based on the non-binary low-density parity-check code (NB-LDPC), to finally determine a power allocation optimization solution that adapts a linear precoding block to an NB-LDPC encoded MIMO transmission. In this paper we use a quadrature amplitude modulation (QAM), over a Rayleigh fading channel with a maximum likelihood detection. Simulations results in term of bit error rate confirmed that NB-LDPC codes are particularly well suited to be jointly used with precoding schemes based on the maximization of the minimum Euclidean distance criterion.

A Novel Iterative Reliability-Based Majority-Logic Decoder for NB-LDPC Codes

Non-binary low-density parity-check (NB-LDPC) codes usually exhibit much better performance than their binary counterparts. Among NB-LDPC decoding algorithms, the iterative reliability-based majority-logic decoding (MLGD) algorithms are attractive for their low computation complexity, at the cost of performance degradation. In this brief, based on the improved iterative soft reliability-based (IISRB)-MLGD algorithm, we propose a clipped-modified (CM)-IISRB algorithm, which achieves better decoding performance with lower computational complexity. First, two modifications are introduced to the IISRB algorithm, which considerably reduces the decoding complexity with negligible performance loss. Second, an unsaturated-clipping method that facilitates significant performance improvement is presented. Simulation results show that the new algorithm outperforms the IISRB by about 0.2dB for the 256-ary (255, 175) example code. Moreover, based on a new storage reduction method, an optimized architecture is developed for the CM-IISRB algorithm. Synthesis results demonstrate that the proposed decoder can achieve very low hardware complexity, comparable to that of the iterative hard reliability-based (IHRB) decoder.

Variable-Length Coding With Shared Incremental Redundancy: Design Methods and Examples

Variable-length (VL) coding with feedback is a commonly used technique that can approach point-to-point Shannon channel capacity with a significantly shorter average codeword length than fixed-length coding without feedback. This paper uses the inter-frame coding of Zeineddine and Mansour, originally introduced to address varying channel-state conditions in broadcast wireless communication, to approach capacity on point-to-point channels using VL codes without feedback. The per-symbol complexity is comparable to decoding the VL code with feedback (plus the additional complexity of a small peeling decoder amortized over many VL codes) and presents the opportunity for encoders and decoders that utilize massive parallel processing, where each VL decoder can process simultaneously. This paper provides an analytical framework and a design process for the degree distribution of the inter-frame code that allows the feedback-free system to achieve 96% or more of the throughput of the original VL code with feedback. As examples of VL codes, we consider non-binary (NB) low-density parity-check (LDPC), binary LDPC, and convolutional VL codes. The NB-LDPC VL code with an 8-bit CRC and an average codeword length of 336 bits achieves 85% of capacity with four rounds of ACK/NACK feedback. The proposed scheme using shared incremental redundancy without feedback achieves 97% of that performance or 83% of the channel capacity.

An Improved Symbol-Flipping Algorithm for Nonbinary LDPC Codes and its Application to NAND Flash Memory

This paper proposes a novel symbol-flipping decoding (SFD) algorithm called decision-symbol reliability-based SFD (DRB-SFD) algorithm for nonbinary low-density parity-check (LDPC) codes aiming to improve the error-rate performances of data storage devices with hard-decision channel outputs, e.g., data storage using NAND flash memory. The proposed algorithm generates the reliability information of decision symbols based on a metric for symbol flipping during iterations instead of soft-decision channel outputs. In addition, it quantizes the reliability information into reliability messages that are exchanged between variable and check nodes. The number of quantization levels is carefully chosen to be the same as the field size of coded symbols, which allows the message exchanges to be performed without the additional signal paths. It is also extensively discussed how to decide parameters in the proposed algorithm in an analytic way. We demonstrate that the proposed algorithm featured with the exchanges of reliability messages provides significant performance improvements over existing SFD algorithms on channels with hard-decision outputs.

Efficient decoding approach for NB‐LDPC codes with short blocklength

In this study, the authors propose a parallel concatenated decoding (PCD) scheme for short non-binary low-density-parity-check (NB-LDPC) codes. It consists of a reduced trellis extended min-sum (R-TEMS) algorithm which efficiently reduces the check node updating complexity over high-order Galois fields and a low complexity ordered statistic decoding aided by partial cyclic redundancy check bits. The R-TEMS algorithm has a negligible performance loss and noticeable reduction in decoding complexity with respect to the trellis-based EMS (TEMS) algorithm. Besides, the PCD shows a close error-correction performance when compared with other concatenated decoding schemes for NB-LDPC codes. It achieves a coding gain about 0.5 dB with reasonable complexity contrasted with the Q-ary sum–product algorithm for high-rate short NB-LDPC codes over GF(256).

A 2.4-mm2 130-mW MMSE-Nonbinary LDPC Iterative Detector Decoder for 4 $\times$ 4 256-QAM MIMO in 65-nm CMOS

Iterative detection and decoding (IDD) employs a soft-in soft-out (SISO) detector and an SISO forward error correction (FEC) decoder in an iterative loop to improve the receiver performance in multiple-input multiple-output (MIMO) wireless communications. This paper describes a 256-QAM 4 × 4 prototype IDD design made up of a minimum mean square error (MMSE) detector and a nonbinary low-density parity-check (NBLDPC) decoder with the symbol size of the NBLDPC code matched to the modulation to enhance performance. By directly translating between nonbinary symbols and constellation points, the detector-decoder interface is simplified. We present a Gb/s MMSE detector using a shortened tandem scheduling, a low-latency dual-lookup reciprocal unit, an optimized interleaved microarchitecture, and a Gb/s NBLDPC decoder with efficient internal skipping paths and memory allocation. The designs were demonstrated in a 0.7-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> 1.38-Gb/s MMSE detector and a 1.7-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> 1.02-Gb/s-NBLDPC decoder that are integrated in a 65-nm CMOS test chip. The chip is measured to achieve 19.2 pJ/b in detection and 20.1 pJ/b/iteration in decoding.

Short Non-Binary Low-Density Parity-Check Codes for Phase Noise Channels

This work considers the design of short non-binary low-density parity-check (LDPC) codes over finite fields of order m, for channels with phase noise. In particular, m-ary differential phase-shift keying (DPSK) modulated code symbols are transmitted over an additive white Gaussian noise (AWGN) channel with Wiener phase noise. At the receiver side, non-coherent detection takes place, with the help of a multi-symbol detection algorithm, followed by a non-binary decoding step. Both the detector and decoder operate on a joint factor graph. As a benchmark, finite length bounds and information rate expressions are computed and compared with the codeword error rate (CER) performance, as well as the iterative threshold of the obtained codes. As a result, performance within 1:2 dB from finite-length bounds is obtained, down to a CER of 1e-3.

Fast-Converging Flipping Rules for Symbol Flipping Decoding of Non-Binary LDPC Codes

Fast-Converging Flipping Rules for Symbol Flipping Decoding of Non-Binary LDPC Codes

Half-row modified two-extra-column trellis min-max decoder architecture for nonbinary LDPC codes

In this paper, a novel half-row modified two-extra-column trellis min-max (HR-mTEC-TMM) algorithm and a corresponding decoder architecture for nonbinary low-density parity-check (NB-LDPC) codes are proposed to greatly reduce the hardware complexity. Because the algorithm processes a half-row at a time, the hardware complexity of the decoder is reduced by almost 50%. The HR-mTEC-TMM algorithm, which keeps only two elements with the highest reliabilities in each extra column, is proposed for the check node unit (CNU) to reduce the memory storage and facilitate the design for the half-row decoder architecture. A layered decoder architecture corresponding to the HR-mTEC-TMM algorithm for the (837, 726) NB-LDPC code over GF(32) is implemented using 90-nm CMOS technology. The implementation results show that the proposed decoder achieves a great area reduction: 28.3% and 41% for the CNU and the whole decoder, respectively. Moreover, the proposed decoder can operate at a clock frequency of 591 MHz and obtains a throughput of 1.15 Gbps.

A Combinatorial Methodology for Optimizing Non-Binary Graph-Based Codes: Theoretical Analysis and Applications in Data Storage

Non-binary (NB) low-density parity-check (LDPC) codes are graph-based codes that are increasingly being considered as a powerful error correction tool for modern dense storage devices. Optimizing NB-LDPC codes to overcome their error floor is one of the main code design challenges facing storage engineers upon deploying such codes in practice. Furthermore, the increasing levels of asymmetry incorporated by the channels underlying modern dense storage systems, e.g., multi-level Flash systems, exacerbate the error floor problem by widening the spectrum of problematic objects that contribute to the error floor of an NB-LDPC code. In a recent research, the weight consistency matrix (WCM) framework was introduced as an effective combinatorial NB-LDPC code optimization methodology that is suitable for modern Flash memory and magnetic recording (MR) systems. The WCM framework was used to optimize codes for asymmetric Flash channels, MR channels that have intrinsic memory, in addition to canonical symmetric additive white Gaussian noise channels. In this paper, we provide an in-depth theoretical analysis needed to understand and properly apply the WCM framework. We focus on general absorbing sets of type two (GASTs) as the detrimental objects of interest. In particular, we introduce a novel tree representation of a GAST called the unlabeled GAST tree, using which we prove that the WCM framework is optimal in the sense that it operates on the minimum number of matrices, which are the WCMs, to remove a GAST. Then, we enumerate WCMs and demonstrate the significance of the savings achieved by the WCM framework in the number of matrices processed to remove a GAST. Moreover, we provide a linear-algebraic analysis of the null spaces of WCMs associated with a GAST. We derive the minimum number of edge weight changes needed to remove a GAST via its WCMs, along with how to choose these changes. In addition, we propose a new set of problematic objects, namely oscillating sets of type two (OSTs), which contribute to the error floor of NB-LDPC codes with even column weights on asymmetric channels, and we show how to customize the WCM framework to remove OSTs. We also extend the domain of the WCM framework applications by demonstrating its benefits in optimizing column weight 5 codes, codes used over Flash channels with additional soft information, and spatially coupled codes. The performance gains achieved via the WCM framework range between 1 and nearly 2.5 orders of magnitude in the error floor region over interesting channels.

High-Throughput FFT-SPA Decoder Implementation for Non-Binary LDPC Codes on x86 Multicore Processors

Low-Density Parity-Check (LDPC) codes are a well known Error Correction Code family used for instance, in wireless and satellite communication links. Error correction performance of LDPC codes was further enhanced by extending it to higher order Galois fields, giving rise hence to the so-called non-binary LDPC codes (NB-LDPC). Error correction performance improvement (CCSDS 2014) is the main reason behind the adoption by the Consultative Committee for Space Data Systems (CCSDS) of the NB-LDPC codes in the experimental specification for the future next generation uplinks (CCSDS 2014, 2015). The high error correction efficiency for short frames make NB-LDPC codes a good candidate for IoT applications. However, the performance gain comes at the expense of a high decoding computational complexity (CCSDS 2014; Conde-Canencia et al. 2009). In this paper, an x86 multicore NB-LDPC decoder implementation is provided. This decoder that implements the FFT-SPA algorithm provides a throughput improvement of about 1.3 × to 2.7 ×, a latency reduction of more than 95% and a power consumption halved in comparison with the most efficient works on GPU (Graphics Processing Unit) device. Indeed, an efficient memory mapping and computation optimizations on the x86 architecture enable to achieve a higher decoding throughput than the GPU-based in similar experimental setup. Consequently, the throughput efficiency, the low processing latency associated with a low power consumption makes this proposed multicore implementation practical and attractive for real time implementations of NB-LDPC decoders in future SDR or Cloud-RAN systems for CCSDS standard and IoT applications.

Optimized Trellis-Based Min-Max Decoder for NB-LDPC Codes

Non-binary low-density parity-check (NB-LDPC) codes outperform their binary counterparts in many cases. However, an NB-LDPC decoder usually requires excessive hardware resources and memory consumption. The trellis-based min-max decoding algorithm (TMMA), a well-known algorithm proposed in recent years, achieves good tradeoff between decoding performance and hardware complexity. Note that the check node processing unit (CNU) occupies the most hardware consumption. Based on the TMMA, many simplifications for the CNU have been developed with slight performance loss. The current TMMA with L truncations (L-TMMA) is promising for higher hardware efficiency than others. In this brief, based on the L-TMMA, we propose a new CNU design by incorporating algorithmic transformation and architectural optimization to further reduce the hardware complexity and thereby the critical path without any performance degradation. Synthesis results show that the proposed design achieves the lowest hardware consumption and the highest clock frequency with a small latency compared to the state-of-the-arts. Specifically, it saves more than 1/3 hardware resources compared with its original one.

Adaptive Rate-Compatible Non-Binary LDPC Coding Scheme for the B5G Mobile System.

This paper studies an adaptive coding scheme for B5G (beyond 5th generation) mobile system-enhanced transmission technology. Different from the existing works, the authors develop a class of rate-compatible, non-binary, low-density parity check (RC-NB-LDPC) codes, which expresses the strong connection between the algebra-based and graph-theoretic-based constructions. The constructed codes can not only express rate-compatible (RC) features, but also possess a quasi-cyclic (QC) structure that facilitates the encoding implementation. Further, in order to achieve the code rate-adaptive allocation scheme, the authors propose using the K-means++ clustering algorithm to cluster different channel environments, considering various factors that affect channel characteristics. Finally, in order to present the advantages of the adaptive coding scheme, the authors construct a coding scheme for image transmission. The numerical results demonstrate that the developed code can obtain better waterfall performance in a larger code rate range, which is more suitable for data transmission; the adaptive coding transmission scheme can obtain higher reconstructed image quality compared to the fixed code rate-coding scheme. Moreover, when considering unequal error protection (UEP), the proposed scheme can further improve the reconstructed image quality.

BP-LED Decoding Algorithm for LDPC Codes Over AWGN Channels

A new method is presented for low-complexity near-maximum-likelihood (ML) decoding of low-density parity-check (LDPC) codes over the additive white Gaussian noise channel. The proposed method termed belief-propagation–list erasure decoding (BP-LED) is based on erasing carefully chosen unreliable bits performed in case of BP decoding failure. A strategy of introducing erasures into the received vector and a new erasure decoding algorithm are proposed. The new erasure decoding algorithm, called list erasure decoding, combines ML decoding over the BEC with list decoding applied if the ML decoder fails to find a unique solution. The asymptotic exponent of the average list size for random regular LDPC codes from the Gallager ensemble is analyzed. Furthermore, a few examples of irregular quasi-cyclic LDPC as well as randomly constructed regular LDPC codes of short and moderate lengths are studied by simulations and their performance is compared to the tightened upper bound on the LDPC ensemble-average performance and the upper bound on the average performance of random linear codes under ML decoding. A comparison of the BP decoding and BP-LED performance of the WiMAX standard codes and performance of the near-ML BEAST decoding are presented. The new algorithm is applied to decoding a short nonbinary (NB) LDPC code over extensions of the binary Galois field. The obtained simulation results are compared to the tightened upper bound on the ensemble-average performance of the binary image of regular NB LDPC codes.

Extended construction of array‐based non‐binary LDPC codes

Array-based non-binary (NB) low-density parity-check (LDPC) codes are attractive in practice for their advantages in implementation and performance. However, existing construction of array-based NB LDPC codes is only with the prime number cases. In this Letter, the authors extend the array-based construction to composite numbers to give an explicit construction of structured array-based NB LDPC codes with column weights three, four, and five. The resulting codes have girth at least six. The simulation results show that the proposed structured codes perform as well as the random codes constructed by progressive edge-growth algorithm, when decoded with the Q-ary sum product algorithm and the low-complexity weighted bit-reliability-based decoding algorithm.

Protograph Based Low-Density Parity-Check Codes Design With Mixed Integer Linear Programming

An approach to design protograph-based low-density parity-check (LDPC) codes utilizing mixed integer linear programming (MILP) optimization is presented in this paper. The protograph (base graph) cyclic lifting for a class of quasi-cyclic LDPC codes is considered. In general, the short cycles elimination is the primary optimization goal, possibly weighted by a metric of cycles connectivity. A notion of closed walks in the base graph is shown to be a convenient way for representing sources of cycles in the lifted graph. We express the condition for non-existence of a cycle in the lifted graph corresponding to a closed walk in the base graph in the form of a set of linear inequalities. Such inequalities, collected for all closed walks shorter than a desired limit corresponding to girth, form a set of linear constraints. Meanwhile, the longer closed walks can be reflected in a linear objective function of the optimization. The proposed combination of constraints and objective function forms an input to a MILP solver. As a result, a globally optimized code graph can be obtained. The method can be utilized for binary as well as nonbinary LDPC codes. The numerical results show that the constructed codes can outperform similar codes deigned with reference heuristic search methods.