Half-row modified two-extra-column trellis min-max decoder architecture for nonbinary LDPC codes

Abstract

In this paper, a novel half-row modified two-extra-column trellis min-max (HR-mTEC-TMM) algorithm and a corresponding decoder architecture for nonbinary low-density parity-check (NB-LDPC) codes are proposed to greatly reduce the hardware complexity. Because the algorithm processes a half-row at a time, the hardware complexity of the decoder is reduced by almost 50%. The HR-mTEC-TMM algorithm, which keeps only two elements with the highest reliabilities in each extra column, is proposed for the check node unit (CNU) to reduce the memory storage and facilitate the design for the half-row decoder architecture. A layered decoder architecture corresponding to the HR-mTEC-TMM algorithm for the (837, 726) NB-LDPC code over GF(32) is implemented using 90-nm CMOS technology. The implementation results show that the proposed decoder achieves a great area reduction: 28.3% and 41% for the CNU and the whole decoder, respectively. Moreover, the proposed decoder can operate at a clock frequency of 591 MHz and obtains a throughput of 1.15 Gbps.