Noise Figure Of Low Noise Amplifier Research Articles

Low Noise Amplifier at 60 GHz Using Low Loss On-Chip Inductors

This paper proposes the technique of using low loss on-chip inductors in the design of low noise amplifier (LNA) that offers high gain and lower noise figure. Upon the substrate of octagonal spiral inductors, a surface of patterned ground shield is inserted that significantly reduces the substrate loss. This effect limits the penetration of electric filed into the substrate, thereby improving the inductor’s Quality (Q) factor and decouples the substrate parasitic that results with smaller series resistance. These effects result with improved gain and noise figure of LNA at 60 GHz when the designed inductors are included in it to serve as gate, source, and load inductances. The proposed work uses an inductively degenerated 3-stage common-source LNA in a 65-nm CMOS process. Simulation results show that the LNA using custom designed inductors achieves the peak gain of 17.02 dB at 56 GHz with a noise figure of 5 dB at 60 GHz for the power consumption of 10 mW. The figure-of-merit (FOM) is 14.56 which is 0.8 times more than the LNA design using off-chip inductors. A complete LNA layout using custom designed inductor footprints has been presented and analyzed.

Inductor-less PVT robust gain switching balun LNA for multistandard applications

ABSTRACTAn inductor-less single to differential low-noise amplifier (LNA) is proposed for multistandard applications in the frequency band of 0.2–2 GHz. The proposed LNA incorporates noise cancellation and voltage shunt feedback configuration to achieve minimum noise characteristics and low power consumption. In addition to noise cancellation, trans-conductance of common-source stage is scaled to improve the noise performance. In this way, noise figure (NF) of LNA below 3 dB is achieved. An additional capacitor Cc is used to correct the gain and phase imbalance at the output. The gain switching has been enabled with a step size of 4 dB for high linearity and power efficiency. The bias point of all transistors is chosen such that the variation in gm is not more than 10%. The proposed LNA is implemented in UMC 0.18-μm RF CMOS technology. The core area is 182 μm × 181 μm. Moreover, the LNA has better ratio of relevant performance to area. The proposed balun LNA is validated by rigorous Monte Carlo simulation. The 3σ deviation of gain and NF is less than 5%. Finally, the proposed LNA is robust to unavoidable PVT variations.

Synthesis Technique for Low-Loss mm-Wave T/R Combiners for TDD Front-Ends

A time-division duplex (TDD) transmit/receive (T/R) millimeter-wave (mm-wave) front-end comprises a power amplifier (PA), a low-noise amplifier (LNA), an antenna switch, and appropriate passive matching and combining networks. In this paper, a synthesis methodology is proposed that minimizes the overall losses by combining the PA output and the LNA input matching networks together with the T/R switch into one network. The technique improves mm-wave transceiver performance in terms of PA efficiency and LNA noise figure. The proposed T/R combiner can achieve high linearity and can handle large PA output voltage swings. The architecture can be implemented in any process which provides high integration capability. A Ka-band implementation is demonstrated using 45 nm CMOS silicon-on-insulator that includes a high power, four-stack-based PA and an inductively source-degenerated cascode-based LNA. Within the front-end, the PA achieves saturated output power of 23.6 dBm with peak power added efficiency of 28%, while the LNA achieves NF of 3.2 dB. The overall chip area is 0.54 mm2, including pads.

A +25-dBm IIP3 1.7–2.1-GHz FDD Receiver Front End With Integrated Hybrid Transformer in 28-nm CMOS

A highly linear receiver (RX) front end with integrated hybrid transformer (HT) for frequency-division duplexing mobile communications is reported. The HT, implemented with a three-winding coplanar transformer, is used to interface the RX front end with the antenna and the power amplifier. The primary is driven at its center tap with the transmitted signal and at one input with the antenna signal, while the other input is connected to an on-chip programmable balancing impedance. The two secondary drives a differential push–pull common-gate low-noise amplifier (LNA). Assuming a perfectly linear hybrid only 45 dB of transmitter (TX)–RX isolation and 35 dB of common-mode rejection are required to meet the intermodulation specs thanks to the +25-dBm receiver IIP3. This would drastically simplify hybrid balancing and adaptation loop. Cascaded noise figure of duplexer, LNA, and baseband is below 6.7 dB and TX insertion loss below 4.3 dB from 1.7 to 2.1 GHz. The implemented prototype in 28-nm CMOS has an active area of 0.7 mm2 and requires only 26 mW.

Transmitter leakage cancellation technique for CMOS SAW-less radio front-ends

A novel method of transmitter (TX) leakage cancellation is presented to improve the dynamic range of the receiver for wideband code division multiple access applications. The large TX leakage is attenuated within the low noise amplifier (LNA) output using a feed-forward path without any LNA noise figure degradation. A prototype has been designed and laid out in 0.18 μm CMOS technology. It achieves a maximum TX rejection of 18.5 dB with only 5.2 mA current consumption from 1.8 V supply voltage. LNA P-1dBCP (1 dB gain compression point) against TX leakage improves by more than 10 dB. Post layout simulations verify these results. Proposed structure dispels the requirement of off-chip surface acoustic wave filter.

Design and Comparison of Low Power High Gain and Low Noise Figure LNA for ISM Applications

Objectives: This paper represents the design and simulation of LNA (Low Noise Amplifier) for ISM (Industrial, Scientific and Medical) applications operating in the 2.4-2.5 GHz band. Methods/Statistical Analysis: In this paper, a very accurate topology named inductive source degeneration topology has been used to provide low NF (Noise Figure), high S21 (forward gain) and very low Power Consumption (PC). The simulation was made through using Advance Design System (ADS) software. Findings: The proposed work prominence on reduction in Noise Figure with increase in power gain at low power consumption as compared to published previous results at 1.2 V power supply. Improvements: This is done in three steps (three different schematic designs) i.e. start with very basic LNA design to proposed LNA design and presents the comparison of all three designed circuit simulations.

Design of penta-band low noise amplifier with integrated active antenna for vehicular communications

The design and integration of penta-band planar antenna with a low noise amplifier (LNA) for vehicular wireless applications is discussed in this research. By integrating antenna with a LNA, the return loss can be kept low with the increased bandwidth compared with a passive antenna with the same design. The performance of the passive antenna, LNA, and integrated active antenna (IAA) are individually validated with the aid of vector network analyzer. The designed IAA covers navigational frequencies 1.2 and 1.5 GHz, wireless communication frequencies 2.4, 3.3 GHz and dedicated short range communication frequency 5.8 GHz, with LNA gain (>10 dB) and noise figure (<2 dB). The proposed design gives room for simultaneous reception of all the desired frequency bands with better performance for vehicular communications.

Design of Cascaded Common Source Low Noise Amplifier for S-Band using Transconductance Feedback

Background/Objectives: Now-a-days advancements in CMOS technology increase the demand on transceiver design in the aspect of gain, linearity, power, re-configurability and cost-effectiveness. The performance of RF frontend of transceiver system using MOS device are excellent and found to be the par of 3-5 semiconductor technology. Methods/Statistical Analysis: The first component present in transceiver design is Low Noise Amplifier (LNA) which requires high gain, low noise, better input-output matching, low power, good linearity and stability. Trade off between these performances is more complex when transistors operate at reduced supply voltage and reduced power consumption. So many researchers focus to modify the existing topology by adding active/passive feedback elements and/or using current re-use inductors 2,3. But the latter, suffer from large power consumption. Moreover LNA using cascode configuration offers good gain with low power but the circuit has the limitation of output voltage swing 4. So the proposed work focuses on the design of LNA using transconductance feedback in Common Source (CS) configuration circuits. Findings: At RF frequencies, distributed parasitic of the device dominates thus altering the input-output matching characteristics which degrades gain, noise figure and stability of Low Noise Amplifier. So design of multistage LNA with feedback techniques is necessary to increase the gain. The transconductance feedback used in the design of LNA suits well for increase of gain provided if it is properly designed to ensure stability. The proposed work involves the design of MOS based low noise amplifier using single stage and cascaded Common Source (CS) configuration in S-band. By using the transconductance feedback in CS amplifier, the voltage gain is boosted. Using the extracted small signal equivalents, single stage and cascaded CS amplifier with the transconductance feedback are designed and analyzed. Importance of device parasitic like gate to source capacitance, gate to drain capacitance and the output resistance influence the loop gain. This is brought in the design and emphasizes on the proper utilization of these parasitic in LNA design with transconductance feedback. Using a standard 90 nm CMOS process, LNAs have been demonstrated for 2-GHz frequency (S-band) applications. Operated at a supply voltage of 0.6 V, the gain and noise figure of single stage CS LNA with transconductance feedback are observed to be 17.9 dB and 2.1 dB respectively. It is noted that nearly 17% gain improvement has been achieved with excellent input reflection coefficient of -54.8 dB and low power consumption of 2.92 mW. Similarly, for a cascaded CS amplifier when operated at 0.6V, it is observed that the gain and noise figure are found to be 13.6 dB and 2.38 dB respectively. It is noted that nearly 6.25% increase in gain is achieved with appealing reverse gain of -52. 8 dB when compared to cascaded CS circuit without transconductance feedback. Higher reverse gain ensures the stability of the designed amplifier. Applications: The proposed work is needed in the design of transceivers working at S-band (2 GHz - 8 GHz). Few noticeable applications are: Communication satellites (NASA), weather radar systems, microwave ovens and optical communication which require low power modules. Improvements: This work can be further extended to reconfigure the input matching network so that UWB bandwidth is covered.

Design and Simulation of Low Noise Amplifier at 10 GHz By GaN High Electron Mobility Transistor

In this paper, design and simulation of a 10 GHz Low Noise Amplifier (LNA) for Wireless communication systems have been explored. The simulation result has been performed by using the Agilent Advanced Design System (ADS) software. Tuning and optimization tools of ADS software have been used to optimize results. The High Electron Mobility Transistor (HEMT) based on GaN is used for decreasing of Minimum Noise Figure (NFmin) of LNA. Also, for more decreasing NFmin of LNA radial stub elements are implemented in biasing network. We have designed a 10 GHz LNA based on three design manner basing on the lumped, the distributed and radial stub elements. The designed amplifier offers forward gain of 15.72 dB with the noise figure of 1.09 dB at 10 GHz. The input return loss (S11) is equal to -9.635 dB at 10GHz. The output return loss (S22) is equal to -10.009 dB at 10GHz. Also, the isolation (S12) of proposed structure is equal to -22 dB at 10 GHz. The simulation result have shown that the forward gain and noise figure of 10 GHz LNA are optimized noticeably with respect to the pervious works.

Ku-대역 광대역 디지탈 위성방송용 저 잡음하향변환기 개발

본 논문에서는 디지털 위성방송을 수신하기 위하여 Ku-대역 광대역 하향변환기를 설계하였다. 설계된 저 잡음 하향변환기는 잡음 정합에 의한 3단 저 잡음 증폭회로와 10.7~12.75 GHz의 입력신호를 VCO-PLL에 의한 저 위상잡음을 나타내는 4개의 국부발진주파수(9.75, 10, 10.75 및 11.3 GHz)를 형성하고, 디지털 제어에 의하여 4-대역의 IF 주파수 채널을 선택할 수 있도록 설계하였다. 개발한 저 잡음 하향 변환기의 전체 변환이득 64 dB, 저 잡음 증폭기의 잡음지수는 0.7 dB, 출력신호의 P1dB는 15 dBm, band 1 반송주파수 9.75 GHz에서 위상잡음은 -85 dBc@10 kHz를 나타내었다. 설계한 광대역 디지털 위성방송용 하향변환기(LNB)는 국제적으로 이동하는 선박 등의 위성방송용으로 사용가능하다. In this paper, wideband Ku-band downconverter was designed to receiver digital satellite broadcasting. The low-nose downconverter was designed to form four local oscillator frequencies(9.75, 10, 10.75 and 11.3 GHz) representing a low phase noise due to VCO-PLL with respect to input signals of 10.7 to 12.75 GHz and 3-stage low noise amplifier circuit by broadband noise matching, and to select intermediate frequency bands by digital control. The developed low-noise downconverter exhibited the full conversion gain of 64 dB, and the noise figure of low-noise amplifier was 0.7 dB, the P1dB of output signal 15 dBm, and the phase noise -85 dBc@10kHz at the band 1 carrier frequency of 9.75 GHz. The low noise block downconverter(LNB) for wideband digital satellite broadcasting designed in this paper can be used for global satellite broadcasting LNB.

글로벌형 다중대역 디지털 위성방송용 Ku-대역 LNB 개발

In this paper, a Multi-Band Ku-band down converter was designed for reception of multi-band digital satellite broadcasting. The Multi-band low-nose down converter was designed to form four local oscillator frequencies (9.75, 10, 10.75 and 11.3GHz) representing a low phase noise due to VCO-PLL with respect to input signals of 10.7 to 12.75GHz and 3-stage low noise amplifier circuit by broadband noise matching, and to select an one band of intermediate frequency (IF) channels by digital control. The developed low-noise downconverter exhibited the full conversion gain of 64dB, and the noise figure of low-noise amplifier was 0.7dB, the P1dB of output signal 15dBm, and the phase noise -73dBc@100Hz at the band 1 carrier frequency of 9.75GHz. The low noise block downconverter (LNB) for receiving four-band digital satellite broadcasting designed in this paper can be used for satellite broadcasting of vessels navigating international waters.

고입력 내성을 위한 GaN HEMT 기반 S-대역 저잡음 증폭기

Abstract In this paper, we present design and measurement of LNA(Low Noise Amplifier) based on GaN HEMT(Gallium Nitride High Electron Mobility Transistor) to reduce the total noise figure of radar receiver and for robustness of LNA. In radar receiver using LNA based on GaAs(Gallium Arsenide) technology, limiter is necessary at the very front of the radar receiver to protect LNA. As a result, total noise figure of radar receiver is deteriorated. In this research, measured noise figure of LNA based on GaN HEMT is below 2 dB. In the case of commercialized GaAs LNA, recommended maximum input power is about 30 dBm. On the other hand, GaN HEMT LNA which is designed and measured is burned-out when input power is 43 dBm and robustness is guaranteed at input power 45.4 dBm. Key words: LNA, GaN HEMT, Robustness, Current Limit ‡wxˆ3‰Š 5wx‹9Œ wx . Ž ‘+C’“(Department of Wireless Communications Engineering,, Kwangwoon University) *ˆ3‰Š(Samsung Thales, Co, Ltd) `Manuscript received December 24, 2014 ; Revised February 5, 2015 ; Accepted February 6, 2015. (ID No. 20141224-105)`Corresponding Author: Jin-Joo Choi (e-mail: jinchoi@kw.ac.kr)

Low‐noise and high‐gain wideband LNA with g m ‐boosting technique

A broadband low-noise amplifier (LNA) is proposed. The active gm -boosting technique is utilised to reduce the common-gate (CG) LNA noise figure and improve gain. An implemented prototype using 0.13 μm CMOS technology is evaluated using on-wafer probing. S 11 and S 22 are below − 10 dB across 0.1–5 GHz. Measurements show a power gain of 18.3 dB with a − 3 dB bandwidth from 100 MHz to 2.1 GHz and an IIP3 of − 7 dBm at 2 GHz. The measured noise figure is better than 2.5 dB below 2.1 GHz, better than 4.5 dB below 5 GHz and at 500 MHz it obtains its minimum value 1.8 dB. The LNA consumes 14 mW from 1.5 V supply and occupies an area of 0.04 mm2.

Rate Gain Region and Design Tradeoffs for Full-Duplex Wireless Communications

In this paper, we analytically study the regime in which practical full-duplex systems can achieve larger rates than an equivalent half-duplex systems. The key challenge in practical full-duplex systems is uncancelled self-interference signal, which is caused by a combination of hardware and implementation imperfections. Thus, we first present a signal model which captures the effect of significant impairments such as oscillator phase noise, low-noise amplifier noise figure, mixer noise, and analog-to-digital converter quantization noise. Using the detailed signal model, we study the rate gain region, which is defined as the region of received signal-of-interest strength where full-duplex systems outperform half-duplex systems in terms of achievable rate. The rate gain region is derived as a piece-wise linear approximation in log-domain, and numerical results show that the approximation closely matches the exact region. Our analysis shows that when phase noise dominates mixer and quantization noise, full-duplex systems can use either active analog cancellation or base-band digital cancellation to achieve near-identical rate gain regions. Finally, as a design example, we numerically investigate the full-duplex system performance and rate gain region in typical indoor environments for practical wireless applications.

Sensitivity of narrow- and wideband LNA performance to individual transistor model parameters

Although it is desirable for a transistor model to be as accurate as possible, the extraction of model parameters from fabricated transistors is a time-consuming and often costly process. An investigation of the sensitivity of low-noise amplifier (LNA) performance characteristics to individual parameters of the physics-based standard HBT model HICUM/L2 was, therefore, done to gain a preliminary insight into the most important parameters for transistors used in actual circuits. This can potentially allow less strenuous accuracy requirements on some parameters which would ease the extraction process. Both a narrow- and wideband LNA configuration were investigated. It was found that the series resistance parameters have a large impact on LNA gain, S 11 and noise figure performance in both cases. Since the narrow-band LNA relied heavily on the transistor characteristics to provide a proper matching, it was also very sensitive to changes in the parameters used in modelling the high-frequency current gain and depletion capacitances of the transistor.

Study on Performance Analysis of CMOS RF front-end circuits for 2.4GHz Wireless Applications

In this paper, low voltage design concepts and new CMOS front-end circuits for 2.4GHz wireless applications are presented. The performances of these circuits are analysed and compared with other existing structures using TSMC 0.18-μm CMOS technology scale. The design trade-offs between impedance matching, power gain and noise figure of low-noise amplifiers are highlighted. The advantage of the introduced mixer topology is expressed in terms of conversion gain, noise figure and linearity. At a supply voltage of 1.8V, the design and performance analysis have been performed using Agilent’s Advanced Design System (ADS2009) software.

A 1.2 V Reactive-Feedback 3.1–10.6 GHz Low-Noise Amplifier in 0.13 $\mu{\hbox {m}}$ CMOS

A 15.1 dB gain, 2.1 dB (min.) noise figure low-noise amplifier (LNA) fabricated in 0.13 mum CMOS operates across the entire 3.1-10.6 GHz ultrawideband (UWB). Noise figure variation over the band is limited to 0.43 dB. Reactive (transformer) feedback reduces the noise figure, stabilizes the gain, and sets the terminal impedances over the desired bandwidth. It also provides a means of separating ESD protection circuitry from the RF input path. Bias current-reuse limits power consumption of the 0.87mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> IC to 9 mW from a 1.2 V supply. Comparable measured results are presented from both packaged and wafer probed test samples

Analytical Expression Based Design of a Low-Voltage FD-SOI CMOS Low-Noise Amplifier

We propose a design methodology of a low-voltage CMOS low-noise amplifier (LNA) consisting of a common-source and a common-gate stages. We first derive equations of power gain, noise figure (NF) and input third-order intercept point (IIP3) of the two-stage LNA. A design methodology of the LNA is presented by using graphs based on analytical equations. A 1-V 5.4-GHz LNA was implemented in 0.15-μm fully-depleted silicon-on-insulator (FD-SOI) CMOS technology. Measurement results show a power gain of 23 dB, NF of 1.7 dB and IIP3 of -6.1 dBm with a power consumption of 8.3 mW. These measured results are consistent with calculated results, which ensures the validity of the derived equations and the proposed design methodology.

Measurement and modeling errors in noise parameters of scaled-CMOS devices

Noise parameter measurements of submicrometer scaled-CMOS devices are error prone. These errors can propagate to a device model affecting the performance of low-noise amplifiers (LNAs) designed with them. In this paper, measurement errors in noise parameters of submicrometer scaled-CMOS devices are quantified. The sensitivity of different noise parameters to measurement and modeling errors is examined, showing that some parameters (NF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> ,R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sub> ) are more immune to such errors than others (G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">opt</sub> ,B <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">opt</sub> ). We propose a modeling and design approach (desensitization by R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sub> -optimization) that can greatly alleviate the impact of such errors on the noise figure of LNAs. Measured results from a 90-nm LNA show substantial (ges 2.5 dB) improvement in its noise figure as a result of desensitization

A resonant switch for LNA protection in watt-level CMOS transceivers

An integrated resonant switch designed to protect low-noise amplifier (LNA) circuits in CMOS transceivers is reported. The design implements the receive-path portion of a transmit/receive switch protecting 3-V-process transistors from 5 W (22-V peak) transmit signals while simultaneously helping to achieve a good LNA noise figure on receive and low power loss on transmit. Since the approach is to combine an LNA's matching network and switch functions, the design has no traditional insertion loss on receive. The effective loss to the transmitted signal is less than 0.5 dB using moderate quality inductors (Q>6) and 0.1 dB using Q=12 inductors achievable in most RF-aware CMOS silicon-on-insulator foundries at UHF through S-band frequencies.