NMOS Capacitors Research Articles

Direct tunneling stress-induced leakage current in ultrathin HfO2∕SiO2 gate dielectric stacks

The conduction mechanism(s) and behavior of direct tunneling stress-induced leakage current (SILC) through ultrathin hafnium oxide (HfO2)/silicon dioxide (SiO2) dual layer gate stack in metal-oxide-semiconductor (MOS) devices have been experimentally investigated in-depth. Both transient and steady-state SILCs have been studied after constant voltage stress (CVS) and constant current stress (CCS) in n-MOS capacitors with negative bias on the tantalum nitride (TaN) gate. The present report clearly indicates that the observed steady-state SILC is due to assisted tunneling via both monoenergetic trapped positive charges and neutral electron traps generated in the HfO2 layer during either CVS or CCS. SILC measured immediately after stress decays slowly due to tunnel detrapping of stress-induced trapped holes in the HfO2 layer. Furthermore, the mechanisms for stress-induced charge carrier generation/trapping and trap creation in the dielectric have been discussed. Our analysis also shows that CVS degrades the dielectric integrity more severely than CCS in the 4.2nm physically thick HfO2∕SiO2 stack.

Characterization of 4H-SiC MOSFETs with NO-Annealed CVD Oxide

Deposited oxide is an attractive gate oxide due to absence of carbon at the MOS interface. We fabricated and characterized Si-face 4H-SiC n-MOS capacitors and n-channel MOSFETs with CVD oxide annealed in NO at 1250°C and compared to those with dry thermal oxide. Nitrogen and carbon distribution in the oxide was evaluated by SIMS. The CVD/NO sample has lower interface state density near the conduction band edge, higher nitrogen concentration at the interface and lower carbon concentration in the oxide than the Dry/NO sample. Channel mobility of 27.7cm 2 /Vs was obtained for the CVD/NO sample, which is higher than the Dry/NO sample (24.9cm 2 /Vs). These MOSFET performances are correlated with the results of n-MOS capacitors and SIMS measurements.

Effect of deposition chemistry and annealing on charge in HfO/sub 2/ stacks

Charge in HfO/sub 2/ gate stacks grown from various metal-organic chemical vapor deposition sources has been studied using nMOS capacitors with a damage-free Cr gate process. It is found that the charge in the stack is mainly concentrated at the interfaces between materials. The effect of postdeposition anneal depends on the high-/spl kappa/ film-deposition chemistry. A forming gas anneal can reduce interface charge, hysteresis, and interface state densities for HfO/sub 2/ films grown from various sources. The marked difference in the annealing response of similar films deposited from different precursors, however, strongly suggests that charge in these stacks is related to the deposition chemistry and may be due to residual impurities or defects left in the film from the deposition.

Hole confinement at Si/SiGe heterojunction of strained-Si N and PMOS devices

Due to the Fermi level pinning effect on the hole confinement at the valence band offset, the capacitance–voltage ( C– V) characteristics of NMOS capacitor exhibit more obvious plateau than that of PMOS capacitor, demonstrated by both experimental and simulated results. Using device simulation, the ratio of hole density at the oxide/strained-Si interface to that at the strained-Si/relaxed SiGe interface for both N and PMOSFETs is investigated. The much higher hole density ratio in PMOSFETs than that in NMOSFETs also reveals the Fermi level pinning effect.

A Study on Charge Reduction in HfO<tex>$_2$</tex>Gate Stacks

Charge in metal-organic chemical vapor deposition-grown HfO/sub 2/ gate stacks has been systematically studied using nMOS capacitors. It is found that, for these films, the charge in the stack is mainly concentrated at the interfaces between the layers and is negative at the HfO/sub 2//interfacial layer (IL) interface and positive at the Si/IL interface. In general, the calculated charge densities at both interfaces are of order 10/sup 12/ cm/sup -2/. A forming gas anneal (FGA) reduces both interface charge greatly. The FGA can also significantly reduce the hysteresis and interface state density. The effects of post deposition anneal at various temperatures and under various ambients have also been studied. It is found that a high-temperature dilute oxidizing ambient anneal followed by an FGA reduces the charge at both interfaces.

Manufacturing Benefits of Disilane as a Precursor for Polycrystalline Silicon Films for the Advanced CMOS Gate Electrode

The polycrystalline silicon deposited by single-wafer rapid thermal chemical vapor deposition with both silane (SiH/sub 4/) and disilane (Si/sub 2/H/sub 6/) precursors have been characterized for across wafer uniformity, thickness repeatability, and basic material properties such as grain structure and surface topography. The results show that the disilane process greatly improves the manufacturability of the single-wafer polycrystalline silicon process. Specifically, a /spl sim/50% improvement in the thickness uniformity, /spl sim/25% improvement in surface roughness, and a significantly less sensitivity of the process to hardware have been achieved with similar particle performance. The grain structure of as-deposited and postimplant and anneal films have been compared by X-ray diffraction and transmission electron microscope. NMOS and PMOS capacitors have been fabricated with polycrystalline silicon using silane and disilane precursors. The grain structure and electrical parameters, such as gate leakage currents and gate capacitance, show no significant difference between these two precursors.

Effect of Shield Line on Noise Margin and Refresh Time of Planar DRAM Cell for Embedded Application

In this paper we investigate the effect of a shield metal line inserted between adjacent bit lines on the refresh time and noise margin in a planar DRAM cell. The DRAM cell consists of an access transistor, which is biased to 2.5V during operation, and an NMOS capacitor having the capacitance of 10fF per unit cell and a cell size of 3.63 µm2. We designed a 1Mb DRAM with an open bit-line structure. It appears that the refresh time is increased from 4.5 ms to 12 ms when the shield metal line is inserted. Also, it appears that no failure occurs when Vcc is increased from 2.2 V to 3 V during a bump up test, while it fails at 2.8 V without a shield metal line. Raphael simulation reveals that the coupling noise between adjacent bit lines is reduced to 1/24 when a shield metal line is inserted, while total capacitance per bit line is increased only by 10%.

Proton radiation effects in 4H-SiC diodes and MOS capacitors

Proton irradiation is used to probe the physics of 4H-silicon carbide (SiC) Schottky barrier diodes (SBDs) and negative channel metal oxide semiconductor (nMOS) capacitors for the first time. Both 4H-SiC SBD diodes and SiC MOS structures show excellent radiation tolerance under high-energy, high-dose proton exposure. Unlike for SiC JBS diodes, which show a strong increase in series resistance after proton irradiation, these SiC SBDs show very little forward bias I--V degradation after exposure to 63.3 MeV protons up to a fluence of 5/spl times/10/sup 13/ p/cm/sup 2/. An improvement in reverse leakage current after irradiation is also observed, which could be due to a proton annealing effect. The small but observable increase in blocking voltage for these SiC SBDs is attributed to a negative surface charge increase, consistent with earlier gamma results. The resultant Q/sub eff/ change of 4H-SiC nMOS capacitors under proton irradiation was used to quantify the radiation induced changes to the blocking voltage in the SBD diodes in MEDICI simulations, and showed a good agreement with the experimental data. Characterization of these capacitors also suggests that 4H-SiC MOS structures are radiation hard.

Reliability of Nitrided Oxides in N- and P-type 4H-SiC MOS Structures

AbstractTDDB measurements of NMOS capacitor fabricated with 1200°C dry oxide with 1300°C N2O anneal were performed at 175°C and 300°C under high positive bias stress. The devices are biased into strong accumulation mode such that the field in the oxide is high enough to collect breakdown data in a reasonable period of time. We observe that at 175°C, a 100-year Mean Time to Failure (MTTF) is obtained at an electric field of 3 MV/cm in the oxide. The TDDB measurement has also been performed at 300°C where lifetime has been reduced by a few orders of magnitude, but with an acceptable 100-year MTTF. Recent reliability results on similarly oxidized MOSFETs have shown failures along the same trend as the n-type capacitors, indicating that MOSFETs and MOS capacitors can have similar reliability despite inherent processing and structural differences. PMOS capacitors fabricated with the aforementioned dry + N2O process as well as capacitors fabricated using the low DIT nitridation techniques show acceptable MTTF of 100 years at the nominal operating electric field of 3 MV/cm.

Interfacial defect states in HfO/sub 2/ and ZrO/sub 2/ nMOS capacitors

A comprehensive analysis of the bump/kink observed in the experimental capacitance-voltage (C-V) curves of HfO/sub 2/ and ZrO/sub 2/ capacitors was performed using self-consistent numerical simulations. Both HfO/sub 2/ samples grown by sputter deposition and grown by metal-organic chemical vapor deposition (MOCVD) were examined. The bumps in the C-V curves were found to be consistent with an interface state centered 0.25 eV above the valence bandedge for the sputter deposited devices, and 0.30 eV above the bandedge for the MOCVD devices. Annealing of the HfO/sub 2/ devices reduced the densities of these traps, but also increased the effective oxide thickness. Similar defect states were detected for the ZrO/sub 2/ devices centered 0.25 eV above the valence bandedge.

Gate oxide properties investigated by TOF-SIMS profiles on CMOS devices

Dynamic secondary ion mass spectrometry (SIMS) is commonly considered an important analytical technique to study the materials used for microelectronics. Direct analyses on electrically tested structures are hard to perform because of strict requirements on raster size and because of poor depth resolution on multi-layer stacks. Time of flight SIMS has been recently applied to this field and developed to perform depth profiles with competitive features. The aim of this work is to show that TOF-SIMS can be directly used to characterize finished devices. By measuring n-MOS capacitors of full processed wafers (raster size up to 12 μm×12 μm ), we studied the Cl contamination introduced by chemical vapor deposition of WSi 2. The comparison between depth profiles and electrical data explained the observed gate oxide behavior.

Numerical simulation of quantum effects in high-k gate dielectric MOS structures using quantum mechanical models

In this paper the electrical characteristics of metal oxide semiconductor (MOS) capacitors with high-k gate dielectric are investigated with quantum mechanical models. Both the self-consistent Schrodinger–Poisson (SP) model and the density gradient (DG) model are solved simultaneously to study quantum confinement effects (QCEs) for MOS capacitors. A computationally efficient parallel eigenvalue solution algorithm and a robust monotone iterative (MI) finite volume (FV) scheme for the SP and DG models are systematically proposed and successfully implemented on a Linux cluster, respectively. With the developed simulator, we can extract the effective gate oxide thickness from capacitance voltage (C-V) measurements for TaN and Al gate NMOS capacitors with Zr O2 and Si O2 gate dielectric materials. We found that quantization effects of 5.0 nm Zr O2 MOS samples cannot be directly equivalent to commonly quoted effects of 1.5 nm Si O2 MOS samples. Achieved benchmarks are also included to demonstrate excellent performances of the proposed computational techniques.  2002 Elsevier Science B.V. All rights reserved.

Photonic high-frequency capacitance-voltage characterization of interface states in metal-oxide-semiconductor capacitors

A new characterization method based on the photonic high-frequency capacitance-voltage (HF C-V) response of metal-oxide semiconductor (MOS) capacitors is reported for the analysis of interface states in MOS systems. An optical source with a photon energy less than the silicon band-gap (h/spl nu/ = 0.799 eV < E/sub g/ = 1.11 eV) is employed for the photonic characterization of interface states (Bit) distributed in the photoresponsive energy band (E/sub c/ h/spl nu/ < E/sub it/ < E/sub c/) in NMOS capacitors with a polysilicon gate. Assuming a uniform distribution of the trap levels, the density of interface states (D/sub it/) was observed to be D/sub it/ 1-5 /spl times/ 10/sup 11/ eV/sup -1/ cm/sup -2/ in the photoresponsive energy band.

Characteristics of TaOxNy Gate Dielectric with Improved Thermal Stability

We report the properties of novel gate dielectric TaOxNy prepared by low-pressure chemical vapor deposition using Ta(OC2H5)5 and NH3. The metal-oxide-semiconductor (MOS) characteristics of TaOxNy/SiO2 gate dielectric are compared with those of Ta2O5/SiO2 stack gated with a W/WN electrode. The flat-band voltage shift (ΔVfb) of TaOxNy in comparison with Ta2O5 is -0.17 V due to the nitrogen-induced positive charges accumulated at the SiO2/Si interface. The interface state density of W/WN/TaOxNy/SiO2/p-Si nMOS capacitors as determined by the conductance method is in the 0.85–1.5×1011 eV-1 cm-2 range near the Si midgap. The leakage current level of the TaOxNy/SiO2/p-Si MOS capacitor is ∼-10 nA/cm2 at -2.5 V at the effective oxide thickness (Teff) of 31 Å. The leakage current is four to five orders of magnitude lower than that of poly-Si-gated SiO2 in the -2–-3 V range. The reliable characteristics of TaOxNy over Ta2O5 in terms of a smaller increase in Teff and excellent breakdown field against selective oxidation at 950°C allow us to maintain the standard complementary metal-oxide-semiconductor fabrication process and technology.

Understanding the effects of wave function penetration on the inversion layer capacitance of NMOSFETs

A comprehensive analysis of the effects of wave function penetration on the capacitance of NMOS capacitors has been performed for the first time, using a self-consistent Schrodinger-Poisson solver. The study reveals that accounting for wave function penetration into the gate dielectric causes carrier profile to be shifted closer to the gate dielectric reducing the electrical oxide thickness. This shift increases with increasing gate voltage. For example, in one simulation, the peak is shifted by about 0.2 nm at a surface field of 1.96 MV/cm and 0.33 nm at a surface field of 3.7 MV/cm. This shifting results in all increased capacitance. The increase in capacitance observed in the inversion region is relatively insignificant when a poly gate electrode with a doping of less than 1/spl times/10/sup 20/ cm/sup -3/ is used due to the poly-depletion effect. A physical picture of the effect of physical thickness on the tunneling current is also presented.

Comparison of soft-breakdown triggers for large-area capacitors under constant voltage stress

This work quantitatively compares soft breakdown identification methods for constant voltage stress of large-area nMOS capacitors (up to 10 mm/sup 2/) with 1.8- to 12-nm gate-oxide thickness (with negative gate voltage). We conclude that in the studied range, breakdown is identified more reliably with a current step trigger than through increased current fluctuation. We present a method to quantify the system background noise, and show results of data filtering algorithms that significantly enhance the ratio between the breakdown signal and background noise level.

High-k Dielectrics and Dual Metal Gates: Integration Issues for New CMOS Materials

ABSTRACTSeveral metal and conducting metal nitride candidates were investigated for alternative gate electrode applications in future complimentary metal-oxide-semiconductor (CMOS) devices. High frequency capacitance-voltage (CV) measurements were performed on n-MOS and p-MOS capacitors with Al, Ta, TaN, TIN, or W2N gates and ultra-thin SiO2/Si3N4 dielectric stacks. The work functions of Al and Ta were close to the conduction band of Si as expected while all the metal nitrides had work functions slightly above mid-gap. The thermal stability of the metal nitrides and the metal/dielectric interfaces was studied by Auger electron spectroscopy (AES) following rapid thermal annealing (RTA). Integration requirements for dual metal gate electrodes in future CMOS devices are discussed.

Theoretical analysis of kink effect in C-V characteristics of Indium-implanted NMOS capacitors

Experimental observation of an anomalous effect in C-V characteristics of Indium-doped NMOS capacitors is reported and explained, for the first time, via the impact of incomplete ionization of Indium. A new analytical formulation of the total semiconductor capacitance is developed, that takes incomplete ionization phenomenon into account. Thanks to this new C/sub SC/(/spl phi//sub s/) relation, we have demonstrated that the carrier freeze-out is responsible for this kink near V/sub FB/ in C-V curves, and also for an intrinsic lowering in the threshold voltage. This kink has been shown to be very sensitive to Indium dose and temperature. It is also demonstrated that the deformation of the C-V characteristics due to Indium incomplete ionization may be (and probably has often been) miss-interpreted as appearance of high fixed charge densities in parameter extraction from C-V fitting. Our analysis is in full agreement with experimental results.

Reverse L-shape sealed poly-buffer LOCOS technology

A description is presented of a new LOCOS (local oxidation of silicon) isolation process, reverse-L-shaped sealed poly-buffer LOCOS (RLS-PBL), which can effectively eliminate the bird's beak without introducing defects. In this process, the pad oxide film is selectively etched, using the silicon nitride/polysilicon stack as a mask to form undercut portions. Thermal oxidation is then performed to grow a new thin oxide film to cover the entire silicon surface, including the undercut portions, in order to provide a new stress-buffer oxide film prior to a thin silicon nitride deposition. The reverse-L-shape sealed silicon nitride spacer is formed by RIE etching. Reverse leakage currents of NMOS submicrometer MOSFET devices, edge diodes, and capacitors fabricated by the new isolation process are comparable to those of conventional LOCOS and poly-buffer LOCOS, and are much superior to those of sealed-interface LOCOS. The defect-free mechanism and nearly zero bird's beak characteristics are attributed to the stress-absorption polycrystalline film in conjunction with the special reverse-L-shape silicon nitride spacer design.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

6173. Surface preciption of boron nitrate on the surface of type 304]' stainless steels doped with nitrogen, boron, and cerium

SiGe alloys are currently used for HBT and MOS as epitaxial layers for base or strained channel, respectively. In the poly phase, SiGe has been studied as a replacement for poly-Si in MOS gates due to its lower thermal budget and gate depletion and also due to the Workfunction Engineering for Vt adjustments. However, for application to CMOS technology as poly-SiGe gates, others constrains emerge such as quality of the oxide interface and etch chemistry. For both applications, the Ge fraction normally lies between 20% and 40%. In this study, authors use a low Ge contents (1%) poly-SiGe thin films aiming for MOS gate electrode. The Ge fraction was determined by RBS analysis. 230 nm thick samples were deposited onto 10 nm thermally oxidized 〈1 0 0〉, p-type Si substrates using silane and germane. Films were deposited in the temperature of 500 °C and total pressure of 667 Pa (5 Torr) by vertical LPCVD. The samples were doped using 31P+ ion implantation from 5 × 1014 cm−2 up to 2 × 1016 cm−2 and annealed by RTP (40 s) from 500 °C up to 900 °C. Rs values were obtained by 4-point probe technique and CV curves were extracted from nMOS capacitors with 200 μm diameter. The same processing steps were used to fabricate similar poly-Si samples and capacitors for comparison.The poly-SiGe samples presented Rs values one order of magnitude lower than poly-Si and CV analysis of nMOS capacitors showed very good characteristics. The 1% Ge in the alloy ensures a low thermal budget for the overall process. Although a relatively high annealing temperature (800 °C) must be used to reduce oxide charge and interface traps, the temperature is well below the necessary for poly-Si processing and can allow formation of the shallow junctions needed for next technological nodes.