This paper reports on one of the first demonstrations of the formation and metallization of 2–5- $\mu \text{m}$ lines and spaces by an embedded trench method in two dry-film polymer dielectrics, Ajinomoto build-up film and preimidized polyimide, without using chemical mechanical planarization. The trenches and vias in 8–15- $\mu \text{m}$ -thick dry-film dielectrics were formed by 308-nm excimer laser ablation, followed by the metallization of the trenches and vias by copper electrodeposition. A low-cost planarization process was used to remove the copper overburden with a surface planer tool. Using an optimized set of materials and processes, multilayer redistribution layers with 2– $5~\mu \text{m}$ trenches and vias were successfully demonstrated. Although thin film processes on silicon wafers have been able to achieve 40- $\mu \text{m}$ I/O pitch for interposers, the materials and processes integrated in this paper are scalable to large panel fabrication at much higher throughput, for interposers and high-density fan-out packaging at lower cost and higher performance than silicon interposers.
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