Nikhilam Sutra Research Articles

Design of energy efficient N-bit vedic multiplier for low power hardware architecture

ABSTRACT In this paper, we introduce an advanced design of an N-bit Vedic multiplier using Nikhilam Sutra and Karatsuba algorithms, tailored for low power hardware architectures. Our approach innovatively combines these ancient mathematical techniques to significantly enhance computational efficiency in digital systems. The primary novelty of our method lies in its capability to drastically reduce both power consumption and operational delay. Compared to conventional multipliers, our design demonstrates an average area reduction of 56% and a latency reduction of 45%. Additionally, the integration of the Karatsuba algorithm optimises the structural design of the multiplier, further lowering the requirements for computational units. This dual-sutra approach not only optimises energy efficiency but also enhances overall effectiveness, making it highly suitable for image and signal processing as well as biomedical applications where power efficiency is crucial. By explicitly stating these key advancements, we aim to clearly communicate the significant strides our research has made in the field of energy-efficient hardware design.

CONTROL STRATEGY FOR REGENERATIVE BRAKING IN ELECTRIC VEHICLES

Abstract—In this paper, a high-speed 32-bit single precision Floating Point Unit (FPU) using Vedic mathematics is proposed. In a general processor, the division architecture plays a crucial role in deciding the overall speed of the system. However, the standard algorithms are sequential units and reduce the performance of the processor. Vedic Mathematics onthe other hand offers a new holistic approach to realizing these operations in a combinational unit. In the proposed architecture an optimized binary division architecture using Nikhilam Sutra is realized. The proposed method is coded in Verilog High Description Language (HDL), synthesized for Artix 7 Field-Programmable Gate Array (FPGA) board, and simulated using Xilinx Vivado Design Suite. Keywords:-Floating- points, Vedic maths, Nikhilam Sutra.

FPGA Implementation of Enhanced Throughput Design of AES Architecture using Nikhilam Sutra

The exponential growth of the internet and contemporary communications users have established safety as a fundamental design feature for encrypted transmission. The Enhanced Cryptography Standard is perhaps the most widely used cryptography information security algorithm standard that has been authorized by NIST. This paper proposes a high-throughput design for the AES Algorithm with huge key sizes. AES would be a block cipher that ensures data security by using key lengths of 128,192 and 256-bits. The design concept focuses on a 256-bit key size classification algorithm since a big key size is required to ensure excellent security. Additionally, simultaneous key expansion & encryption/decryption processes would be pipelined to maximize speed. Parallelization of a key expansion module's sub-processes would be used to reduce the critical chain latency. The S-box comprising sub-byte & inverse sub-byte operations has been developed with compound field arithmetic operations to reduce time and area further. The work Increased throughput by 50%, area reduced by 34.32 %, and latency by 20% compared to the old approach with modified nikhilam sutra. Additionally, integrated AES encryption/decryption is planned and implemented on the FPGA Zed board utilizing Verilog HDL in Xilinx Vivado.

VLSI Design Based Delay and Power Performance Comparison and Analysis of Multipliers

Recently, the problem of power dissipation has become more important in VLSI design. The multiplier is a major drain on resources. The multiplier is a basic operation in arithmetic. This article examines a variety of multipliers at the algorithmic, circuit, and layout levels. The multiplier schematic was designed using TANNER TOOL. It has been possible to increase the speed and area of multipliers by utilising Vedic mathematics for multiplication. Vedic mathematics' "Ni khilam sutra" formula can multiply large numbers. One of the primary objectives is to increase speed while simultaneously decreasing power, area, and delay.

Fast signed multiplier using Vedic Nikhilam algorithm

Vedic algorithm is beneficial for the application in the design of high-speed computing and hardware. This study presents a fast signed binary multiplication structure based on Vedic Nikhilam algorithm. The authors explored the Nikhilam sutra for unsigned decimal numbers to both signed decimal and binary operands. The proposed multiplier leads to significant gains in speed by converting a large operand multiplication to small operand multiplication, along with addition. The proposed design is synthesised with Xilinx ISE 14.4 software and realised using different field programmable gate array devices. The efficiency of the proposed design depends on combinational delay, area and power. Moreover, the new multiplier architecture achieves speed improvement over prior design.

Double Precision Floating Point Fft Processor using Vedic Mathematics

There should be rapid, efficient and simple process for every scenario now a day. To compute the N point DFT, Fast Fourier Transform (FFT) is a productive algorithm. It has great applications in communication, signal and image processing and instrumentation. In the implementation of FFT one of the challenges is the complex multiplications, so to make this process rapid and simple it’s necessary for a multiplier to be fast and power efficient. To tackle this problem Karatsuba sutra and Nikhilam sutra are an efficient method of multiplication in Vedic Mathematics. This paper will present a design methodology of Double Precision Floating Point Fast Fourier Transform (FFT) Processor.The execution time and complexity can be reduced by the algorithm which is there in Vedic.The main aim is to make FFT Processor process rapid and simple by designing a multiplier which is fast and power efficient by using double precision floating point and Vedic Mathematics concepts.

A Delay Efficient Vedic Multiplier

Vedic mathematics is the ancient Indian method of mathematics based on 16 Sutras applicable to various branches of mathematics like trigonometry, calculus, geometry, conics etc. Multiplication is effectively used in modern communication and Digital Signal Processing applications. Ordinary multiplication requires propagation of carry from LSB to MSB while adding binary partial products, which limits the overall speed of multiplication. Vedic mathematics helps in generation of partial products and sums in one step, and ensures reduction in overall propagation delay. Urdhva Tiryakbhyam Sutra and Nikhilam Sutra are the two multiplication techniques used in Vedic mathematics. In this paper, an 8 * 8 Nikhilam Sutra multiplier for three different sets of bases is realized. The concepts of Urdhva Tiryakbhyam Sutra multiplication are used for the implementation of the proposed multiplier. The implementation results are compared with that of a Modified Booth’s multiplier in terms of delay, area and power. The design is synthesized in Synopsys Design Compiler using CMOS 90 nm technology, and results show that the proposed multiplier using Nikhilam Sutra with 25 bases is faster than the Modified Booth’s multiplier by 51.28%.

VLSI design for efficient RSD-Based ECC processor using Karatsuba algorithm

In this paper, an exportable application-particular direction set elliptic bend cryptography processor in view of repetitive marked digit portrayal is proposed. The processor utilizes broad pipelining strategies for Karatsuba– Of man strategy to accomplish high throughput augmentation. Moreover, an effective particular viper without correlation and a high throughput measured divider, which brings about a short data path for expanded recurrence, are actualized. The proposed design of this paper investigation the rationale size, region and power utilization utilizing Xilinx 13.2. The expansion for the task is Vedic Sutra – Nikhilam Sutra.

Design of High Speed Vedic Multiplier based on Nikhilam Sutra Algorithm using Successive Approximation

The mathematical system followed in the Ancient India is Vedic Mathematics. It helps to calculate the arithmetic operations faster without any computerized system. Vedic Mathematics works on the principles of Sutra. It deals with mathematics linked with arithmetic, algebra, and geometry. These modus operandi and ideas can be directly applied to trigonometry, plain and spherical geometry, conics, differential calculus, integral calculus and applied mathematics of different kinds. There are various multipliers among them Urdhva Triyakbyam Sutra is used widely because it dissipates less power and area efficient multiplier. Nikhilam sutra is not widely used due to its limitations in the calculation of remainder. In this paper, high speed Vedic multiplier is designed by modifying Nikhilam sutra principles using bit reduction technique. In the calculation of remainder in Vedic multiplier based on Nikhilam Sutra, the addition and subtraction is done with the base value of 10 for decimal number system. For binary multiplication, base 2 is considered and 2’s complement is taken to derive the remainder in the algorithm. In this work, the remainder is calculated using bit reduction technique to reduce the complexity of the multiplier. The first two bits are reduced from the given N-bit number. Hence, the multiplier size is reduced to N-2 for remainder multiplication. Additionally, shift operations are needed to perform the multiplication of two N-bit binary numbers. By the successive application of this multiplier, higher bit length multiplier can be easily designed with less computation time. The proposed algorithm is implemented using mentor Graphics tool. The results are compared N-bit conventional multipliers and the proposed method. Comparing with conventional methods, the Wallace multiplier is the fastest multiplier. While comparing with conventional Nikhilam multiplier and Urdhva Triyakbyam multiplier, our proposed multiplier gives the result in minimum computation time. While comparing with Wallace and our proposed gives the optimum result. The proposed design is suitable for high speed compact size arithmetic applications.

Design of an Efficient Binary Vedic Multiplier for High Speed Applications Using Vedic Mathematics with Bit Reduction Technique

Vedic mathematics is the system of mathematics followed in ancient Indian and it is applied in various mathematical branches. The word “Vedic” represents the storehouse of all knowledge. Because using Vedic Mathematics, the arithmetical problems are solved easily. The mathematical algorithms are formed from 16 sutras and 13 up-sutras. But there are some limitations in each sutra. Here, two sutras Nikhilam sutra and Karatsuba algorithm are considered. In this research paper, a novel algorithm for binary multiplication based on Vedic mathematics is designed using bit reduction technique. Though Nikhilam sutra is used for multiplication, it is not used in all applications. Because it is special in multiplication. The remainder is derived from this sutra by reducing the remainder bit size to N-2 bit. Here, the number of bits of the remainder is constantly maintained as N-2 bits. By using Karatsuba algorithm, the overall structure of the multiplier is designed. Unlike the conventional Karatsuba algorithm, the proposed algorithm requires only one multiplier with N-2 bits only. The speed of the proposed algorithm is improved with balancing the area and the power. Even though there is a deviation in lower order bits, this method shows larger difference in higher bit lengths.

Implementation of <i>N</i>-Bit Binary Multiplication Using <i>N</i> - 1 Bit Multiplication Based on Nikhilam Sutra and Karatsuba Principles Using Complement Method

This paper is designed to introduce new hybrid Vedic algorithm to increase the speed of the multiplier. This work combines the principles of Nikhilam sutra and Karatsuba algorithm. Vedic Mathematics is the mathematical system to solve the complex computations in an easier manner. There are specific sutras to perform multiplication. Nikhilam sutra is one of the sutra. But this has some limitations. To overcome the limitations, this sutra is combined with Karatsuba algorithm. High speed devices are required for high speed applications with compact size. Normally multipliers require more power for its computation. In this paper, new multiplication algorithm for the multiplication of binary numbers is proposed based on Vedic Mathematics. The novel portion in the algorithm is found to be in the calculation of remainder using complement method. The size of the remainder is always set as N - 1 bit for any combination of input. The multiplier structure is designed based on Karatsuba algorithm. Therefore, N × N bit multiplication is done by (N - 1) bit multiplication. Numerical strength reduction is done through Karatsuba algorithm. The results show that the reduction in hardware leads to reduction in the delay.

Vedic Multiplier in VLSI for High SpeedApplications

Today most of the processor requires very high speed of operation. Usually DSP processors are based on mathematical approaches. In that multiply-accumulate operation plays vital role. Compared to addition, multiplication process takes large amount of time thus reduces the speed of the processor, consumes some amount of power and area. In this paper we proposed two techniques to improve processor speed based on Vedic mathematics. In Vedic mathematics among 16 sutras, 2 sutras are applicable for multiplication. First method URDHAVA TRIYAKBHYAM sutra which is similar to array multiplication .When number of bits increases, gate delay and area increases slowly compared to other multiplier. So the advanced technique called NIKHILAM sutra is employed. These sutras are meant for faster mental calculation. Though faster when implemented in hardware, it consumes more power than the conventional ones. In this project both the techniques are compared and found that nikhilam is best. This project presents a technique to modify the architecture of the Vedic multiplier by using some existing methods in order increase the processor speed.

High speed multiplier using Nikhilam Sutra algorithm of Vedic mathematics

This article presents the design of a new high-speed multiplier architecture using Nikhilam Sutra of Vedic mathematics. The proposed multiplier architecture finds out the compliment of the large operand from its nearest base to perform the multiplication. The multiplication of two large operands is reduced to the multiplication of their compliments and addition. It is more efficient when the magnitudes of both operands are more than half of their maximum values. The carry save adder in the multiplier architecture increases the speed of addition of partial products. The multiplier circuit is synthesised and simulated using Xilinx ISE 10.1 software and implemented on Spartan 2 FPGA device XC2S30-5pq208. The output parameters such as propagation delay and device utilisation are calculated from synthesis results. The performance evaluation results in terms of speed and device utilisation are compared with earlier multiplier architecture. The proposed design has speed improvements compared to multiplier architecture presented in the literature.

Implementation of Power Efficient Vedic Multiplier

multiplier is based on the ancient algorithms (sutras) followed in INDIA for multiplication. This work is based on one of the sutras called Nikhilam Sutra. These sutras are meant for faster mental calculation. Though faster when implemented in hardware, it consumes more power than the conventional ones. This paper presents a technique to modify the architecture of the Vedic multiplier by using some existing methods in order to reduce power. The 32 X 32 Vedic multiplier is coded in Verilog HDL and Synthesized using Synopsys Design Compiler. The performance is compared in terms of area, data arrival time and power with earlier existing architecture of Vedic multiplier. The proposed design shows very good improvements in terms of power.

Synthesis Comparison of Karatsuba Multiplierusing Polynomial Multiplication, Vedic Multiplier and Classical Multiplier

In this paper, the authors have compared the efficiency of the Karatsuba multiplier using polynomial multiplication with the multiplier implementing Vedic mathematics formulae (sutras), specifically the Nikhilam sutra. The multipliers have been implemented using Spartan 2 xc2s200 pq208 FPGA device having speed grade of -6. The proposed Karatsuba multiplier has been found to have better efficiency than the multipliers involving Vedic mathematics formulae. General Terms Karatsuba algorithm, Vedic multiplier, classical multiplication.

Delay-Power Performance Comparison of Multipliers in VLSI Circuit Design

A typical processor central processing unit devotes a considerable amount of processing time in performing arithmetic operations, particularly multiplication operations. Multiplication is one of the basic arithmetic operations and it requires substantially more hardware resources and processing time than addition and subtraction. In fact, 8.72% of all the instruction in typical processing units is multiplication. In this paper, comparative study of different multipliers is done for low power requirement and high speed. The paper gives information of “Urdhva Tiryakbhyam” algorithm of Ancient Indian Vedic Mathematics which is utilized for multiplication to improve the speed, area parameters of multipliers. Vedic Mathematics suggests one more formula for multiplication of large number i.e. “Nikhilam Sutra” which can increase the speed of multiplier by reducing the number of iterations.