Abstract
This paper is designed to introduce new hybrid Vedic algorithm to increase the speed of the multiplier. This work combines the principles of Nikhilam sutra and Karatsuba algorithm. Vedic Mathematics is the mathematical system to solve the complex computations in an easier manner. There are specific sutras to perform multiplication. Nikhilam sutra is one of the sutra. But this has some limitations. To overcome the limitations, this sutra is combined with Karatsuba algorithm. High speed devices are required for high speed applications with compact size. Normally multipliers require more power for its computation. In this paper, new multiplication algorithm for the multiplication of binary numbers is proposed based on Vedic Mathematics. The novel portion in the algorithm is found to be in the calculation of remainder using complement method. The size of the remainder is always set as N - 1 bit for any combination of input. The multiplier structure is designed based on Karatsuba algorithm. Therefore, N × N bit multiplication is done by (N - 1) bit multiplication. Numerical strength reduction is done through Karatsuba algorithm. The results show that the reduction in hardware leads to reduction in the delay.
Highlights
Researchers are trying to design devices which require minimum space and power with high speed
The MAS (Multiplier Adder Subtractor) unit is incorporated [5] in the design of conventional ALU using Vedic Mathematics
The architecture is designed based on the combination of Karatsuba and Nikhilam sutra. in the conventional Karatsuba algorithm, the remainder is determined by taking Least Significant Half of the number without alteration
Summary
Researchers are trying to design devices which require minimum space and power with high speed. The multipliers are the important unit in many high speed applications. It needs more components and consumes more power. Wallace will occupy more space due to the usage of more components [1] To overcome these issues, multiplier based on Vedic Mathematics is designed. The compressor adders are used in the conventional multipliers to validate their proposed work. The MAS (Multiplier Adder Subtractor) unit is incorporated [5] in the design of conventional ALU using Vedic Mathematics. In [9], various conventional multipliers are compared with Vedic multiplier in terms of area, speed and power. In [12], the Vedic multiplier is designed using Nikhilam sutra and Karatsuba algorithm. Without swapping, the multiplication is done through the calculation of remainder using 2’s complement method
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