Abstract
Abstract—In this paper, a high-speed 32-bit single precision Floating Point Unit (FPU) using Vedic mathematics is proposed. In a general processor, the division architecture plays a crucial role in deciding the overall speed of the system. However, the standard algorithms are sequential units and reduce the performance of the processor. Vedic Mathematics onthe other hand offers a new holistic approach to realizing these operations in a combinational unit. In the proposed architecture an optimized binary division architecture using Nikhilam Sutra is realized. The proposed method is coded in Verilog High Description Language (HDL), synthesized for Artix 7 Field-Programmable Gate Array (FPGA) board, and simulated using Xilinx Vivado Design Suite. Keywords:-Floating- points, Vedic maths, Nikhilam Sutra.
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