Neural Amplifier Research Articles

A High Value, Linear and Tunable CMOS Pseudo-Resistor for Biomedical Applications

A subthreshold MOS-based pseudo-resistor featuring a very high value and ultra-low distortion is proposed. A bandpass neural amplifier with a very low high-pass cutoff frequency is designed, to demonstrate the linearity of the proposed resistor. A BJT less CTAT current generator has been introduced to minimize the temperature drift of the resistor and make tuning easier. The standalone resistor has achieved 0.5% better linearity and a 12% improved temperature coefficient over the existing architectures. A neural amplifier has been designed with the proposed resistor as a feedback element. It demonstrated 31[Formula: see text]dB mid-band gain and a low-pass cutoff frequency of 0.85[Formula: see text]Hz. The circuit operates from a 1[Formula: see text]V supply and draws 950[Formula: see text]nA current at room temperature.

Compact, Programmable, Two-Stage Configuration for Implantable Biopotential Recording Amplifiers

This paper proposes an area-efficient CMOS amplifier for neural recording applications. The proposed neural amplifier takes advantage of indirect negative feedback to realize a rather low upper [Formula: see text]3-dB cutoff frequency. As a result, the capacitance needed to realize the cutoff frequency is so small that can be easily implemented on-chip. Moreover, the proposed circuit also employs attenuators in the same feedback loop in order to further reduce the silicon area consumed by the capacitors and at the same time to increase the input impedance of the circuit. Designed based on a two-stage configuration, the amplifier provides tunable lower cutoff frequency and digitally-programmable upper cutoff frequency and voltage gain. The circuit is designed in a 0.18-[Formula: see text]m technology, and consumes 0.022[Formula: see text]mm2 and 0.27[Formula: see text]mm2 of chip areas for single- and eight-channel designs, respectively. Operated with a supply voltage of 1.8[Formula: see text]V, power consumption of the proposed amplifier is 36.7[Formula: see text][Formula: see text]W with the simulated input-referred noise of 4[Formula: see text][Formula: see text] over 1[Formula: see text]Hz–10[Formula: see text]kHz for each channel. The amplifier also provides an output swing of 0.95 Vpp with a total harmonic distortion of [Formula: see text]50[Formula: see text]dB at the frequency of 1[Formula: see text]kHz.

Self-Biased Ultralow Power Current-Reused Neural Amplifier With On-Chip Analog Spike Detections

An ultralow power 0.6 V neural amplifier with on-chip analog spike detection is presented. A capacitively-coupled instrumentation amplifier (CCIA) with the current-reused and self-biased scheme is proposed to reduce the overall power consumption and to enhance the noise efficiency. The transistors in the amplifier are operated in the subthreshold region to enhance noise performance. The analog-domain spike detection based on a low power peak detector can reduce the overall power consumption. The circuit is fabricated using the standard 0.18 μm CMOS process. The passband of the circuit is from 6.4 Hz to 4.46 kHz. Input-referred noise is 10.68 μVrms. The supply voltage is 0.6 V, and the power consumption of the singlestage CCIA is 50.6 nW. The CCIA achieves a good noise efficiency factor and power efficiency factor of 1.79 and 1.93, respectively. The overall power consumption including two CCIAs, the programmable gain amplifier, and the analog spike detector is 269.8 nW. Input spikes with an amplitude of 50 μV at 100-Hz intervals are accurately detected.

Design of high gain, high bandwidth neural amplifier IC considering noise-power trade-off

Low Noise Neural amplifiers are used for amplifying low amplitude neural spikes in Neural recording systems. The need for low noise is emphasized by the presence of background noise during recording. Additionally, the need of more number of recording sites and avoiding of excessive heating has given rise to low area and power requirement. In this paper, the design of a neural amplifier IC consisting of two high performance neural amplifiers for recording action potentials/spikes are proposed. One amplifier is based on capacitive feedback topology and is noise efficient while the other one is based on open loop topology and is area as well as power efficient. Both amplifiers use a self-biased high swing cascode current mirror load based Folded Cascode Operational Transconductance Amplifier (OTA), which results in an efficient performance with a trade-off between noise and power. The use of such a current mirror load in the OTA helps in achieving a better output swing. The use of source degenerated resistors assures current scaling which results in low input referred noise. Simulations have been carried out using technology parameters of SCL 180 nm foundry. Simulation results and comparative analysis illustrate that the proposed closed loop neural amplifier reports a significant improvement in gain, CMRR and bandwidth while the proposed open loop neural amplifier reports an improvement in power dissipation as compared to most of the state of art designs. Monte Carlo analysis is performed which gives a low average standard deviation, which further validates consistency and reliability of both the proposed designs.

Current-Efficient Preamplifier Architecture for CMRR Sensitive Neural Recording Applications.

There are neural recording applications in which the amplitude of common-mode interfering signals is several orders of magnitude higher than the amplitude of the signals of interest. This challenging situation for neural amplifiers occurs, among other applications, in neural recordings of weakly electric fish or nerve activity recordings made with cuff electrodes. This paper reports an integrated neural amplifier architecture targeting in-vivo recording of local field potentials and unitary signals from the brain stem of a weakly electric fish Gymnotus omarorum. The proposed architecture offers low noise, high common-mode rejection ratio (CMRR), current-efficiency, and a high-pass frequency fixed without MOS pseudoresistors. The main contributions of this work are the overall architecture coupled with an efficient and simple single-stage circuit for the amplifier main transconductor, and the ability of the amplifier to acquire biopotential signals from high-amplitude common-mode interference in an unshielded environment. A fully-integrated neural preamplifier, which performs well in line with the state-of-the-art of the field while providing enhanced CMRR performance, was fabricated in a 0.5 m CMOS process. Results from measurements show that the gain is 49.5dB, the bandwidth ranges from 13Hz to 9.8kHz, the equivalent input noise is 1.88 V, the CMRR is 87dB and the Noise Efficiency Factor is 2.1. In addition, in-vivo recordings of weakly electric fish neural activity performed by the proposed amplifier are introduced and favorably compared with those of a commercial laboratory instrumentation system.

Online Artifact Cancelation in Same-Electrode Neural Stimulation and Recording Using a Combined Hardware and Software Architecture.

Advancing studies of neural network dynamics and developments of closed-loop neural interfaces requires the ability to simultaneously stimulate and record the neural cells. Recording adjacent to or at the stimulation site produces artifact signals that are orders of magnitude larger than the neural responses of interest. These signals often saturate the recording amplifier causing distortion or loss of short-latency evoked responses. This paper proposes a method to cancel the artifact in simultaneous neural recording and stimulation on the same electrode. By combining a novel hardware architecture with concurrent software processing, the design achieves neural signal recovery in a wide range of conditions. The proposed system uniquely demonstrates same-electrode stimulation and recording, with neural signal recovery in presence of stimulation artifact 100dB larger in magnitude than the underlying signals. The system is tested both in vitro and in vivo, during concurrent stimulation and recording on the same electrode. In vivo results in a rodent model are compared to recordings made by a commercial neural amplifier system connected in parallel.

Leakage compensation scheme for ultra‐high‐resistance pseudo‐resistors in neural amplifiers

Although MOS-based pseudo-resistors are capable of achieving the ultra-high resistance required to design small-area neural amplifiers, they suffer from substrate leakage currents which become dramatically higher when the devices are exposed to light. This can cause unwanted amplifier offsets and hinders the usability of these devices in the emerging optoelectrical neural applications. A solution is proposed to compensate the pseudo-resistor leakage current using a dummy deep N-well device. Experimental results show that neural amplifiers implemented with the compensated pseudo-resistor become more robust to photo-induced leakage currents.

An implantable mixed-signal CMOS die for battery-powered in vivo blowfly neural recordings

A mixed-signal die containing two differential input amplifiers, a multiplexer and a 50 KSPS, 10-bit SAR ADC, has been designed and fabricated in a 0.35 μm CMOS process for in vivo neural recording from freely moving blowflies where power supplied voltage drops quickly due to the space/weight limited insufficient capacity of the battery. The designed neural amplifier has a 66 + dB gain, 0.13 Hz-5.3 KHz bandwidth and 0.39% THD. A 20% power supply voltage drop causes only a 3% change in amplifier gain and 0.9-bit resolution degrading for SAR ADC while the on-chip data modulation reduces the chip size, rendering the designed chip suitable for battery-powered applications. The fabricated die occupies 1.1 mm2 while consuming 238 μW, being suitable for implantable neural recordings from insects as small as a blowfly for electrophysiological studies of their sensorimotor control mechanisms. The functionality of the die has been validated by recording the signals from identified interneurons in the blowfly visual system.

Design of integrated neural stimulating and recording frontend for bladder control prosthesis

Functional electrical stimulation has been widely used for the restoration of bladder functions after spinal cord injury or other neurological disorders. However, most of the neuroprostheses for bladder control are still imperfect due to lack of the feedback information about the state of the controlled bladder. The purpose of this study is to develop an implantable system which allows us to stimulate the nerves and record the nerve signals related to the condition of the bladder. The proposed stimulator consists of three parts: a digital-to-analog converter (DAC), a current driver, and a switch network. Using the same current source with a switch network eliminates the need for separate current sources for anodic and cathodic sections and reduce the need for interconnect lines of control signals which is an area-saved and power-efficient configuration. A symmetrical regulated cascode current driver is used to implement a high voltage compliance and a high output impedance which improves its ability with load. The amplitude, frequency and the pulse width of the stimulating current are adjusted by encoding the DAC and switch sequences, respectively. In addition, we also present two-stage fully differential capacitively-coupled amplifiers for neural recording. The neural amplifier's parameters are carefully chosen according to the characteristics of neural signal; meanwhile, we analyzed theoretically the main noise sources, especially the pseudo-resistor in the feedback path which gives little attention by previous studies. The integrated neural stimulating and recording frontend for bladder control prosthesis has been designed and simulated, using a TSMC's 0.18-μm CMOS process. The proposed stimulator can provide a symmetrical cathodic-first biphasic current pulse with interphasic gap, a low headroom voltage of 0.168 V corresponding to 2.48 mA full-scale current, an adjustable pulse width of 100---500 μs and frequency of 1---40 Hz. The recording amplifier with a low input-referred noise of 3.62 μV, an NEF of 3.88 and a low power dissipation of 7.2 μW has a gain of 61.6 dB and a frequency bandwidth from 300 Hz to 5.3 kHz. Both circuit analysis and simulations are presented to examine the performance of the proposed designs.

Ultrahigh-Density 256-Channel Neural Sensing Microsystem Using TSV-Embedded Neural Probes.

Highly integrated neural sensing microsystems are crucial to capture accurate signals for brain function investigations. In this paper, a 256-channel neural sensing microsystem with a sensing area of 5 × 5mm 2 is presented based on 2.5-D through-silicon-via (TSV) integration. This microsystem composes of dissolvable μ-needles, TSV-embedded μ-probes, 256-channel neural amplifiers, 11-bit area-power-efficient successive approximation register analog-to-digital converters, and serializers. This microsystem can detect 256 electrocorticography and local field potential signals within a small area of 5mm × 5mm. The neural amplifier realizes 57.8dB gain with only 9.8μW per channel. The overall power of this microsystem is only 3.79 mW for 256-channel neural sensing. A smaller microsystem with dimension of 6mm × 4mm has been also implanted into rat brain for somatosensory evoked potentials (SSEPs) recording by using contralateral and ipsilateral electrical stimuli with intensity from 0.2 to 1.0mA, and successfully observed different SSEPs from left somatosensory cortex of a rat.

A bidirectional neural interface CMOS analog front-end IC with embedded isolation switch for implantable devices

A bidirectional neural interface analog front-end IC with both stimulation and recording functions is implemented using 0.18-µm standard CMOS process. The proposed IC is comprised of a bipolar biphasic neural stimulator using a transistor-stacked current-mirror driver to achieve good current matching performance in stimulation mode and low-voltage capacitive feedback neural amplifiers for recording mode. In order to save die area, high-voltage isolation switches are embedded within the stimulator core to protect the low-voltage recording circuits from damage. Despite using a low-voltage process, the stimulator is able to deliver up to 1mA current through 10kΩ load using 12.8V supply voltage and the recording amplifier uses 0.8V supply voltage while consuming 1µA of current. The complete IC occupies 0.29mm2 of die area and can be applied for various multi electrode array interface bidirectional neural SoCs in medical implant devices.

An universal test station for multichannel integrated neural amplifiers based on LabVIEW environment

An universal test station for multichannel integrated neural amplifiers based on LabVIEW environment

Heterogeneous neural amplifier integration for scalable extracellular microelectrodes.

We here demonstrate multi-chip heterogeneous integration of microfabricated extracellular recording electrodes with neural amplifiers, highlighting a path to scaling electrode channel counts without the need for more complex monolithic integration. We characterize the noise and impedance performance of the heterogeneously integrated neural recording electrodes, and analyze the design parameters that enable the low-voltage neural input signals to co-exist with the high-frequency and high-voltage digital outputs on the same silicon substrate. This heterogeneous integration approach can enable future scaling efforts for microfabricated neural probes, and provides a design path for modular, fast, and independent scaling innovations in recording electrodes and neural amplifiers.

Design considerations for neural amplifiers.

The initial amplification stage is a critical element of a neural signal acquisition system, and the design of low-noise, low-power amplifiers has received a great deal of attention in recent publications. In this paper we discuss practical considerations for the design of amplifiers intended for neural interfaces. Noise is a major issue due to the low amplitude of neural signals. Practical system deployments also require adequate rejection of common-mode interference, such as that due to line power noise or muscle artifacts, and supply noise. This paper attempts to provide some guideance for system and circuit designers and point out opportunities for potential future exploration.

A Fully Integrated Wireless Compressed Sensing Neural Signal Acquisition System for Chronic Recording and Brain Machine Interface.

Reliable, multi-channel neural recording is critical to the neuroscience research and clinical treatment. However, most hardware development of fully integrated, multi-channel wireless neural recorders to-date, is still in the proof-of-concept stage. To be ready for practical use, the trade-offs between performance, power consumption, device size, robustness, and compatibility need to be carefully taken into account. This paper presents an optimized wireless compressed sensing neural signal recording system. The system takes advantages of both custom integrated circuits and universal compatible wireless solutions. The proposed system includes an implantable wireless system-on-chip (SoC) and an external wireless relay. The SoC integrates 16-channel low-noise neural amplifiers, programmable filters and gain stages, a SAR ADC, a real-time compressed sensing module, and a near field wireless power and data transmission link. The external relay integrates a 32 bit low-power microcontroller with Bluetooth 4.0 wireless module, a programming interface, and an inductive charging unit. The SoC achieves high signal recording quality with minimized power consumption, while reducing the risk of infection from through-skin connectors. The external relay maximizes the compatibility and programmability. The proposed compressed sensing module is highly configurable, featuring a SNDR of 9.78 dB with a compression ratio of 8×. The SoC has been fabricated in a 180 nm standard CMOS technology, occupying 2.1 mm × 0.6 mm silicon area. A pre-implantable system has been assembled to demonstrate the proposed paradigm. The developed system has been successfully used for long-term wireless neural recording in freely behaving rhesus monkey.

FPGA Based ASFSRBN Controller for Low Offset Integrator for Long Pulse Operation in Aditya Tokamak

Tokamaks are the most proficient devices for acquiring nuclear fusion energy from high-temperature, ionized gas termed as Plasma. Mostly, tokamaks are utilized the toroidal magnetic plasma component and poloidal magnetic plasma component to retain and automatic control. Similar characteristics of two operational amplifiers should be needed in the integration system to calculate the drift value. Inductive magnetic sensors are routinely utilized on existing Tokamaks, are well comprehended and they oblige signal integration to focus the strength of the magnetic field. However, the signal integration failed to solve the problem of deciding the stability of the controlled systems. The Sample and Hold Amplifier (SHA) is an essential part of the sampling (Analog Devices, 2009) to digital convert (ADC). The proposed method is used for eliminating the offset drift of the Integrator for long pulse operations. Adaptive Self Organizing Fuzzy Radial Basis-Function Neural Network Controller (ASFRBNC) and DAC amplifiers are able to adjust the signal for utilization of the PCS and DAS dynamic ranges. The loop processing has done with MATLAB Simulink process. This tokamak has 100s pulse lengths, oblige integrators with better attributes in drift and noise with the long pulse lengths. The proposed system was implemented in Field Programmable Gate Array (FPGA) chip with the use of Verilog Hardware Description-Language (Verilog HDL). The experimental results shown that the proposed method obtained 745 Slices, 61 Flip-Flops (FF), 46 I/O buffers (IOBs), 1221 4bit Look up Tables (LUT) and synchronized with the maximum 50.36MHz clock frequency. The obtained hardware results have been matched with the MATLAB simulation results.

Low-Frequency Noise and Offset Rejection in DC-Coupled Neural Amplifiers: A Review and Digitally-Assisted Design Tutorial.

We review integrated circuits for low-frequency noise and offset rejection as a motivation for the presented digitally-assisted neural amplifier design methodology. Conventional AC-coupled neural amplifiers inherently reject input DC offset but have key limitations in area, linearity, DC drift, and spectral accuracy. Their chopper stabilization reduces low-frequency intrinsic noise at the cost of degraded area, input impedance and design complexity. DC-coupled implementations with digital high-pass filtering yield improved area, linearity, drift, and spectral accuracy and are inherently suitable for simple chopper stabilization. As a design example, a 56-channel 0.13 [Formula: see text] CMOS intracranial EEG interface is presented. DC offset of up to ±50 mV is rejected by a digital low-pass filter and a 16-bit delta-sigma DAC feeding back into the folding node of a folded-cascode LNA with CMRR of 65 dB. A bank of seven column-parallel fully differential SAR ADCs with ENOB of 6.6 are shared among 56 channels resulting in 0.018 [Formula: see text] effective channel area. Compensation-free direct input chopping yields integrated input-referred noise of 4.2 μVrms over the bandwidth of 1 Hz to 1 kHz. The 8.7 [Formula: see text] chip dissipating 1.07 mW has been validated in vivo in online intracranial EEG monitoring in freely moving rats.

Multichannel Low‐Noise Low‐Power Amplifier for Neural Signal Acquisition

SUMMARYThis paper describes a low‐noise and low‐power spike neural signal amplifier design that has cut‐off frequency compensation between channels and chips. The variation of the frequency characteristics of amplifiers should be minimized among the channels and chips. This is a requirement to perform statistical correlation analysis from a neuroscience‐oriented point of view. Our design includes an adjustable cut‐off frequency using a 4‐bit variable capacitance. After compensation, the variation of the cut‐off frequency was reduced to between –0.4 kHz and +0.3 kHz from between –1.1 kHz and +3.6 kHz; that is, the value before trimming under the condition of a target cut‐off frequency of 10 kHz. We designed a multineural signal amplifier using the Rohm 0.18 m CMOS process. The designed neural amplifier has capacitive coupled differential input to reject large dc offsets generated at the electrode–tissue interface and to avoid strong common mode noise. To achieve high energy efficiency with low noise in order to observe spike signals of the order of a few tens of mV, the MOS transistors in the OTA are operated in the subthreshold region and combined with a low‐pass filter that consumes less than a hundred nW. The amplifier yielded a midband gain of 37.9 dB and the input‐referred noise was measured as 3.76 Vrms with a consumption of 4.30 W, with a 0.9 V power supply. These results correspond to a noise efficiency factor (NEF) of 2.23, close to the limit using a single differential OTA prepared by a CMOS process.

A Low-Power, High CMRR Neural Amplifier System Employing CMOS Inverter-Based OTAs With CMFB Through Supply Rails

Multichannel neural amplifiers are commonly implemented with a shared reference whose input impedance is several times lower than that of the corresponding signal inputs. This huge impedance mismatch significantly degrades the total common mode rejection ratio (TCMRR) regardless of the amplifier’s intrinsic CMRR (ICMRR). This study reports a multichannel neural amplifier system that eliminates this impedance mismatch problem by using single-ended CMOS-inverter-based preamplifiers for both the reference and signal inputs. A common-mode feedback (CMFB) loop through the supply rails of the preamplifiers is implemented to enhance their ac input common mode range to $220\;\text{mV}_\text{pp}$ and their ICMRR to more than 90 dB at low frequencies. The ICMRR is maintained above 80 dB up to 1 kHz by minimizing the load drive mismatch between the signal and reference preamplifiers. Implemented in a CMOS 65 nm process, this 16-channel amplifier system operates at 1 V and consumes $118\; \upmu\text{W}$ . It has input referred noise of $4.13\; \upmu\text{V}_\text{rms}$ , leading to a noise efficiency factor (NEF) and a power efficiency factor (PEF) of 3.19 and 10.17, respectively. In vivo recordings of cortical neurons of a macaque were successfully acquired, demonstrating the ability of the amplifier to acquire neural signals in an unshielded environment.

Implantable neurotechnologies: a review of integrated circuit neural amplifiers.

Neural signal recording is critical in modern day neuroscience research and emerging neural prosthesis programs. Neural recording requires the use of precise, low-noise amplifier systems to acquire and condition the weak neural signals that are transduced through electrode interfaces. Neural amplifiers and amplifier-based systems are available commercially or can be designed in-house and fabricated using integrated circuit (IC) technologies, resulting in very large-scale integration or application-specific integrated circuit solutions. IC-based neural amplifiers are now used to acquire untethered/portable neural recordings, as they meet the requirements of a miniaturized form factor, light weight and low power consumption. Furthermore, such miniaturized and low-power IC neural amplifiers are now being used in emerging implantable neural prosthesis technologies. This review focuses on neural amplifier-based devices and is presented in two interrelated parts. First, neural signal recording is reviewed, and practical challenges are highlighted. Current amplifier designs with increased functionality and performance and without penalties in chip size and power are featured. Second, applications of IC-based neural amplifiers in basic science experiments (e.g., cortical studies using animal models), neural prostheses (e.g., brain/nerve machine interfaces) and treatment of neuronal diseases (e.g., DBS for treatment of epilepsy) are highlighted. The review concludes with future outlooks of this technology and important challenges with regard to neural signal amplification.