Network-on-Chip Research Articles

SeVNoC: Security Validation of System-on-Chip Designs With NoC Fabrics

Modern System-on-Chip (SoC) designs include a variety of Network-on-Chip (NoC) fabrics to implement coordination and communication of integrated hardware intellectual property (IP) blocks. An important class of security vulnerabilities involves a rogue hardware IP interfering with this communication to compromise the integrity of the system. Such interference includes message mutation, misdirection, delivery prevention, or IP masquerading, among others. In this article, we propose a scalable RTL-level SoC validation scheme, SeVNoC, for the systematic detection of security violations in inter-IP communications for SoC designs with NoC fabrics. Given a target security property to be validated, SeVNoC entails extraction of the control-flow graph of the relevant SoC, which is analyzed through a security property-based model comparison, without incurring state-space explosion. Our experiments on full-scale realistic SoC designs with multiple IPs and NoC architecture indicate that SeVNoC detects security violations in NoC communications with near-perfect accuracy, within only a few minutes.

A Framework for Design, Verification, and Management of SoC Access Control Systems

System-on-chip (SoC) architectures are a heterogeneous mix of microprocessors, custom accelerators, memories, interfaces, peripherals, and other resources. These resources communicate using complex on-chip interconnect networks that attempt to quickly and efficiently arbitrate memory transactions whose behaviors can vary drastically depending on the current mode of operation and system operating state. Security- and safety-critical applications require access control policies that define how these resources interact to ensure that malicious and unsafe behaviors do not occur. <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Aker</small> is a design and verification framework for on-chip access control. The core of <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Aker</small> is the access control wrapper (ACW)–a high-performance yet efficient hardware module that dynamically arbitrates on-chip communications. <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Aker</small> distributes ACWs across the SoC and programs them to perform local access control. <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Aker</small> provides a firmware generation tool and a property-driven security verification methodology to ensure that the ACWs are properly integrated and configured. <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Aker</small> security verification confirms that the ACW behaves properly at IP level. It verifies the hardware root of trust firmware configures the ACW correctly. And it evaluates system-level security threats due to interactions between shared resources. <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Aker</small> is experimentally validated on a Xilinx UltraScale+ programmable SoC. Additionally, an <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Aker</small> access control system is integrated into the OpenPULP multicore archtiecture that uses OpenTitan hardware root-of-trust for firmware configuration.

On-Chip Power Integrity Simulation Using LSI-Core Macromodels Considering Voltage Fluctuations Caused by Inter-Function-Block Interference

When designing on-chip power distribution networks (PDNs) of a large-scale integrated circuit (LSI), power integrity (PI) must be ensured not to cause malfunctions. LSI-core macromodels are expected to be used for fast PI simulation. When building LSI-core macromodels from design information, the impedance and equivalent current sources are often extracted for each function block or smaller operating block. In the stage of modeling function blocks, the layout and operation of the surrounding function blocks are not fixed, so equivalent current sources of the macromodel of each function block are extracted under ideal power supply conditions. However, in an actual LSI, the on-chip PDNs have a certain impedance and the power supply voltage of each function block is not ideal dc voltage because of its own operation and the interference from the operation of surrounding function blocks in the same power domain. Since operating currents of transistors are affected by on-chip supply voltage fluctuations, this effect must be taken into account when simulating the PI of the entire LSI or the simulation accuracy will degrade. This article proposes a PI simulation method using LSI-core macromodels that takes into account on-chip supply voltage fluctuations due to the interference between function blocks in the same power domain. To verify the proposed method, a test chip with several function blocks was built, and it was confirmed that the proposed method can simulate PI with high accuracy.

Artificial neural network on-chip and in-pixel implementation towards pulse amplitude measurement

We present the design of an in-pixel artificial intelligence (AI) for extraction of an amplitude of a pulse generated in semiconductor detector. The AI is design with traditional multi-level perceptron scheme having 6 layers and the total number of 420 parameters. The implementation shows 0.34% measurement accuracy. The AI block is fed by the 6-bit ADC at 5 MHz sampling rate. Standard front-end is optimized for low-noise pulses carrying 1000–3000 electrons. The methodology was tested using FPGA and results are promising. The design is intended to be fabricated and verified in the prototype solution.

A Novel Approach for Integrated Shortest Path Finding Algorithm (ISPSA) Using Mesh Topologies and Networks-on-Chip (NOC)

A novel data dispatching or communication technique based on circulating networks of any network IP is suggested for multi data transmission in multiprocessor systems using Networks-On-Chip (NoC). In wireless communication network management have some negatives have heavy data losses and traffic of data sending data while packet scheduling and low performance in the varied network due to workloads. To overcome the drawbacks, in this method proposed system is Integrated Shortest Path Search Algorithm (ISPSA) using mesh topologies. The message is sent to IP (Internet Protocol) in the network until the specified bus accepts it. Integrated Shortest Path Search Algorithm for communication between two nodes is possible at any one moment. On-chip wireless communications operating at specific frequencies are the most capable option for overcoming metal interconnects multi-hop delay and excessive power consumption in Network-on-Chip (NoC) devices. Each node can be indicated by a pair of coordinates (level, position), where the level is the tree's vertical level and the view point is its horizontal arrangement in the sequence of left to right. The output gateway node's n nodes are linked to two nodes in the following level, with all resource nodes located at the bottommost vertical level and the constraint of this topology is its narrow bisection area. The software Xilinx 14.5 tool by using that overall performance analysis of mesh topology, each method are reduced data losses with better accuracy although the productivity of the delay is decreased by 21 % was evaluated and calculated..

MXene-Nanoflakes-Enabled All-Optical Nonlinear Activation Function for On-Chip Photonic Deep Neural Networks.

2D metal carbides and nitrides (MXene) are promising material platforms for on-chip neural networks owing to their nonlinear saturable absorption effect. The localized surface plasmon resonances in metallic MXene nanoflakes may play an important role in enhancing the electromagnetic absorption; however, their contribution is not determined due to the lack of a precise understanding of its localized surface plasmon behavior. Here, a saturable absorber made of MXene thin film and a silicon waveguide with MXene flakes overlayer are developed to perform neuromorphic tasks. The proposed configurations are reconfigurable and can therefore be adjusted for various applications without the need to modify the physical structure of the proposed MXene-based activator configurations via tuning the wavelength of operation. The capability and feasibility of the obtained results of machine-learning applications are confirmed via handwritten digit classification task, with near 99% accuracy. These findings can guide the design of advanced ultrathin saturable absorption materials on a chip for a broad range of applications.

A congestion-aware hybrid SRAM and STT-RAM buffer design for network-on-chip router

Network-on-chip (NoC) offers a scalable and flexible communication infrastructure for many-cores systems. Buffers in router is used for fine-grain flow control and Quality of Service (QoS), yet it is the major contributor of area and power consumption. In this paper, we propose a hybrid buffer design with SRAM and Spin-Torque Transfer Magnetic RAM (STT-RAM) for NoC router leveraging a novel architecture combined Virtual Channel (VC) and Virtual Output Queuing (VOQ) to store congested and uncongested flow separately. Experiments demonstrates that the proposed scheme can achieve 11.8% network performance improvement and 32.9% power saving with only 8.2% area overhead degradation compared to conventional SRAM based buffer design.

Sixer: A low-overhead, fully-distributed test scheme with guaranteed delivery of packets in networks-on-chip

The guaranteed delivery of application packets from source to destination in a network-on-chip (NoC) is increasingly becoming an essential design issue. Channel faults may cause a significant amount of packet loss and subsequently degrade the system’s performance. In particular, open-channel defects threaten the loss of reliability, yield, and service quality. Hence, their detection and localization during the system’s runtime are highly needed. However, coexistent short-channel faults might mitigate the threats to a certain extent. This paper presents a low-cost test method that detects open-channel faults to preserve the connectivity between a source and destination pair in NoCs. The procedure is extended to address the channel’s self-repairing mode by covering the short-channel defects via fault masking. Further, a fully distributed test-scheduling technique named “Sixer” is presented to reduce the test cost and make the scheme scalable with NoCs. Experimental results show hardware synthesis incurs nearly 6.72% and 21.85% area overhead while single and multiple channel-fault models are assumed, respectively. The test method takes 8 and 38 clocks for the same fault models. Also, fault simulation shows full and (nearly 95%) fault coverage for these models. Online evaluation of the “Sixer” reveals various performance metrics. A detailed comparison study shows the proposed scheme improves hardware area and test-time overhead up to 66.12% and 97%, respectively. Simultaneously, performance overhead is improved by 43.78%, 54.75%, and 62.97% concerning packet loss, latency, and energy consumption, respectively.

Optical neural ordinary differential equations.

Increasing the layer number of on-chip photonic neural networks (PNNs) is essential to improve its model performance. However, the successive cascading of network hidden layers results in larger integrated photonic chip areas. To address this issue, we propose the optical neural ordinary differential equations (ON-ODEs) architecture that parameterizes the continuous dynamics of hidden layers with optical ODE solvers. The ON-ODE comprises the PNNs followed by the photonic integrator and optical feedback loop, which can be configured to represent residual neural networks (ResNets) and implement the function of recurrent neural networks with effectively reduced chip area occupancy. For the interference-based optoelectronic nonlinear hidden layer, the numerical experiments demonstrate that the single hidden layer ON-ODE can achieve approximately the same accuracy as the two-layer optical ResNets in image classification tasks. In addition, the ON-ODE improves the model classification accuracy for the diffraction-based all-optical linear hidden layer. The time-dependent dynamics property of ON-ODE is further applied for trajectory prediction with high accuracy.

Perspective on 3D vertically-integrated photonic neural networks based on VCSEL arrays

Abstract The rapid development of artificial intelligence has stimulated the interest in the novel designs of photonic neural networks. As three-dimensional (3D) neural networks, the diffractive neural networks (DNNs) relying on the diffractive phenomena of light, has demonstrated their superb performance in the direct parallel processing of two-dimensional (2D) optical data at the speed of light. Despite the outstanding achievements, DNNs utilize centimeter-scale devices to generate the input data passively, making the miniaturization and on-chip integration of DNNs a challenging task. Here, we provide our perspective on utilizing addressable vertical-cavity surface-emitting laser (VCSEL) arrays as a promising data input device and integrated platform to achieve compact, active DNNs for next-generation on-chip vertical-stacked photonic neural networks. Based on the VCSEL array, micron-scale 3D photonic chip with a modulation bandwidth at tens of GHz can be available. The possible future directions and challenges of the 3D photonic chip are analyzed.

Freely switching between ferroelectric and resistive switching in Hf0.5Zr0.5O2 films and its application on high accuracy on-chip deep neural networks

Freely switching between ferroelectric and resistive switching in Hf0.5Zr0.5O2 films and its application on high accuracy on-chip deep neural networks

Mathematical Modeling of Flow Control Mechanism in Wireless Network-on-Chip

Network-on-chip (NoC) is an effective interconnection solution of multicore chips. In recent years, wireless interfaces (WIs) are used in NoCs to reduce the delay and power consumption between long-distance cores. This new communication structure is called wireless network-on-chip (WiNoC). Compared to the wired links, demand to use the shared wireless links leads to congestion in WiNoCs. This problem increases the average packet latency as well as the network latency. However, using an efficient control mechanism will have a great impact on the efficiency and performance of the WiNoCs. In this paper, a mathematical modeling-based flow control mechanism in WiNoCs has been investigated. At first, the flow control problem has been modeled as a utility-based optimization problem with the wireless bandwidth capacity constraints and flow rate of processing cores. Next, the initial problem has been transformed into a dual problem without limitations and the best solution of the dual problem is obtained by the gradient projection method. Finally, an iterative algorithm is proposed in a WiNoC to control the flow rate of each core. The simulation results of synthetic traffic patterns show that the proposed algorithm can control and regulate the flow rate of each core with an acceptable convergence. Hence, the network throughput will be significantly improved.

Photonic machine learning with on-chip diffractive optics

Machine learning technologies have been extensively applied in high-performance information-processing fields. However, the computation rate of existing hardware is severely circumscribed by conventional Von Neumann architecture. Photonic approaches have demonstrated extraordinary potential for executing deep learning processes that involve complex calculations. In this work, an on-chip diffractive optical neural network (DONN) based on a silicon-on-insulator platform is proposed to perform machine learning tasks with high integration and low power consumption characteristics. To validate the proposed DONN, we fabricated 1-hidden-layer and 3-hidden-layer on-chip DONNs with footprints of 0.15 mm2 and 0.3 mm2 and experimentally verified their performance on the classification task of the Iris plants dataset, yielding accuracies of 86.7% and 90%, respectively. Furthermore, a 3-hidden-layer on-chip DONN is fabricated to classify the Modified National Institute of Standards and Technology handwritten digit images. The proposed passive on-chip DONN provides a potential solution for accelerating future artificial intelligence hardware with enhanced performance.

MRCN: Throughput-Oriented Multicast Routing for Customized Network-on-Chips

The relentless proliferation of Big Data and artificial intelligence has compelled computing platform architectures to evolve into heterogeneous multicores for greater energy efficiency. A customized network-on-chip (NoC) supporting interconnection diversity is pivotal for the asymmetric data-access traffic requirements of modern heterogeneous multicore system-on-chip (SoC). A significant portion of on-chip data access comprises single-source multi-destination (SSMD) traffic, which supports barrier synchronization, multi-threading, cache coherency protocols, and deep neural network (DNN) acceleration. By amortizing SSMD traffic, multicast routing is essential for effectively utilizing communication bandwidth. One of the primary concerns in supporting multicast routing in NoCs is to circumvent the additional deadlock conditions caused by branch operations among the active routers. However, it is challenging to implement the throughput-optimized multicast routing in irregular topology-based NoCs because the deadlock conditions become highly complicated, and the Hamiltonian path required to apply the labeling rule may not exist. Two important observations were identified regarding multicast routing in customized NoCs: 1) Even if the NoC lacks a Hamiltonian path, deadlock-freedom can be guaranteed by restricting branch operations to a specific destination. 2) A variable path diversity in a custom topology can be leveraged in routing path allocation and branch. Based on these properties, this study proposes a deadlock-free and throughput-enhanced multicast routing for customized NoC (MRCN). MRCN ensures deadlock freedom by utilizing extended routing and router labeling rules. Furthermore, destination router partitioning and traffic-aware adaptive branching are incorporated to reduce packet routing hops and disperse channel traffic. The effectiveness of MRCN was verified using Noxim, a well-known cycle-accurate NoC simulator, under various topologies and traffic patterns. The simulation revealed that MRCN improved the average latency by 13.98 % and the throughput by 12.16 % under the saturated traffic conditions over the previous multicast routings in customized NoCs.

A Unified Clock-Gated Error Correction Scheme with Three-Phase Latch-Based Pipeline for Energy-Efficient Wide Supply Voltage Range Router

Network-on-chip (NoC) has played a vital role in enabling high-speed and energy-efficient data communication among different cores in a multi-or many-core System-on-Chip (SoC). To mitigate the pessimistic timing margin reversed for severe process, voltage, and temperature (PVT) variations, we presented a wide supply voltage range router with a novel error detection and correction (EDAC) technique adopted in its latch-based pipeline for high energy efficiency. Especially, a unified clock-gated error correction scheme is presented to address dynamic timing errors under PVT variations and functional pipeline stalls when occurring allocation failure (packet fails to obtain an output port) or flow control (the next router stalls the current packet transmitting) in one cycle. Moreover, a latch-based pipeline structure with three non-overlapped clocks is adopted to further reduce the short-path padding overhead, which is significantly increased in the ultra-low voltage (ULV) regime. Consequently, we prototyped a 2 × 2 2D mesh NoC test chip with 28-nm CMOS technology. Compared with the margined baseline with a 10% VDD drop, measurement results show that the proposed router enables 1.4×, 32.4%, and 7.5% improvements in frequency, energy, and area, respectively. Furthermore, the proposed techniques can reduce packet loss by 200× and increase throughput by 19.9% for the NoC at 0.4 V, 25∘C.

The CTH Network: An NoC Platform for Scalable and Energy Efficient Application Mapping Solution

Multi-threaded design of the applications has given a new dimension to the execution concurrency. The Network-on-Chip (NoC) infrastructure has evolved as the communication backbone in multiprocessor System-on-Chips (MPSoCs) to exploit Thread-Level Parallelism (TLP). Mapping the threads of various applications on the processing cores is crucial in utilizing the resources of a many-core system. An application's performance depends primarily on the mapping strategy. However, the performance of an application gets influenced significantly by the underlying network architecture of the NoC. The present work proposes a run-time application mapping technique based on the Cube-Tree-Hybrid (CTH) topology focusing on the traffic load balancing across the network. The mapping overhead decreased significantly by exploiting the low network diameter of CTH with its high scalability and path diversity, projecting a 31% reduction in normalized execution time over the prevalent algorithms on the existing mapping platforms. Rigorous experimentation with varying application and network sizes is carried out across mesh, ZMesh, torus, and Mest-of-Tree (MoT) networks. The experimental observations project that the proposed algorithm results in sustainable application performance with 15%-21% gain in the overall energy consumption over the existing state-of-the-art techniques across various benchmark workloads.

Fault-Tolerant Spiking Neural Network Mapping Algorithm and Architecture to 3D-NoC-Based Neuromorphic Systems

Neuromorphic computing uses spiking neuron network models to solve machine learning problems in a more energy-efficient way when compared to conventional artificial neural networks. However, mapping the various network components to the neuromorphic hardware is not trivial to realize the desired model for an actual simulation. Moreover, neurons and synapses could be affected by noise due to external interference or random actions of other components (i.e., neurons), which eventually lead to unreliable results. This work proposes a fault-tolerant spiking neural network mapping algorithm and architecture to a 3D network-on-chip (NoC)-based neuromorphic system (R-NASH-II) based on a rank and selection mapping mechanism (RSM). The RSM allows the ranking and rapid selection of neurons for fault-tolerant mapping. Evaluation results show that with our proposed mechanism, we could maintain a mapping efficiency of 100% with 20% spare rate and a fault rate (40%) more than in the previous mapping framework. The Monte Carlo simulation evaluation of reliability shows that the RSM mechanism has increased the mean time to failure (MTTF) of the previous mapping technique by 43% on average. Furthermore, the operational availability of the RSM for mapping to a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4\times 4\times 4$ </tex-math></inline-formula> (smallest) and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6\times 6\times 6$ </tex-math></inline-formula> (largest) NoC is 88% and 67% respectively.

Worst-Case Communication Time Analysis for On-Chip Networks With Finite Buffers

Network-on-Chip (NoC) is the ideal interconnection architecture for many-core systems due to its superior scalability and performance. An NoC must deliver critical messages from a real-time application within specific deadlines. A violation of this requirement may compromise the entire system operation. Therefore, a series of experiments considering worst-case scenarios must be conducted to verify if deadlines can be satisfied. However, simulation-based experiments are time-consuming, and one alternative is schedulability analysis. In this context, this work proposes a schedulability analysis to accelerate design space exploration in real-time applications on NoC-based systems. The proposed worst-case analysis estimates the maximum latency of traffic flows assuming direct and indirect blocking. Besides, we consider the size of buffers to reduce the analysis’ pessimism. We also present an extension of the analysis, including self-blocking. We conduct a series of experiments to evaluate the proposed analysis using a cycle-accurate simulator. The experimental results show that the proposed solution presents tighter results and runs four orders of magnitude faster than the simulation.

NCDE: In-Network Caching for Directory Entries to Expedite Data Access in Tiled-Chip Multiprocessors

The processing of data-intensive applications, followed by an unprecedented amount of data traffic, drives explosive accesses to the memory subsystem. The overloaded memory subsystem experiences increased data access latency. To expedite data access, a network caching technique that leverages network-on-chip (NoC) virtual channels (VCs) as an expanded memory subsystem has emerged. Previous network caching studies focused on utilizing VCs on the NoC’s local input port as a victim cache to reduce local data access latency. In contrast to previous studies, we explore the opportunity of mitigating problems associated with shared data access via in-network caching for directory entries (NCDE), which can utilize every input port’s VCs to hold directory entries. NCDE exploits VCs as the victim and prefetch buffers of the directory entries, each reducing directory eviction-induced invalidations and simplifying the cache-to-cache (C2C) data transfer. The effectiveness of NCDE was evaluated using a gem5 full-system simulator, and the results show that the average memory access time (AMAT) and workload execution time were reduced by 7.69% and 5.82%, respectively. As a cost for accelerating the data access latency, implementing NCDE incurs a negligible router area overhead of 1.56%.

On-Chip Optical Switching Network Architecture Based on Hybrid Wavelength and Mode Division Multiplexing

On-Chip Optical Switching Network Architecture Based on Hybrid Wavelength and Mode Division Multiplexing