Network-on-Chip Research Articles

PKCA: A priori‐knowledge and congestion‐awareness method for adaptive routing algorithms in mesh architectures

AbstractAdaptive routing algorithms have been widely utilized in Network‐on‐Chip (NoC) architectures and have shown to enhance overall throughput in numerous studies. The adaptive routing algorithms can effectively detect network congestion. On the one hand, one‐hop awareness or local awareness can easily detect network congestion but may also result in local greed. On the other hand, global awareness is better for load balancing, but it is difficult to be aware of the network congestion status. This article proposes a lightweight adaptive on‐chip routing algorithm based on the concentric circles theory and prior knowledge derived from real‐life observations. The algorithm, named the Priori‐Knowledge and Congestion‐Awareness method (PKCA), aims to optimize the routing efficiency within the chip. PKCA is designed to be not only simple but also to have low time complexity, allowing it to calculate paths to destinations without local greed. We performed evaluations, and the results demonstrated that our design surpasses one‐hop awareness, two‐hop awareness, and global awareness by 31%, 25%, and 20%, respectively, in terms of latency, and by 22%, 14%, and 22%, respectively, in terms of throughput. Furthermore, the time complexity is only in an 2D mesh.

On-chip spiking neural networks based on add-drop ring microresonators and electrically reconfigurable phase-change material photonic switches

We propose and numerically demonstrate a photonic computing primitive designed for integrated spiking neural networks (SNNs) based on add-drop ring microresonators (ADRMRs) and electrically reconfigurable phase-change material (PCM) photonic switches. In this neuromorphic system, the passive silicon-based ADRMR, equipped with a power-tunable auxiliary light, effectively demonstrates nonlinearity-induced dual neural dynamics encompassing spiking response and synaptic plasticity that can generate single-wavelength optical neural spikes with synaptic weight. By cascading these ADRMRs with different resonant wavelengths, weighted multiple-wavelength spikes can be feasibly output from the ADRMR-based hardware arrays when external wavelength-addressable optical pulses are injected; subsequently, the cumulative power of these weighted output spikes is utilized to ascertain the activation status of the reconfigurable PCM photonic switches. Moreover, the reconfigurable mechanism driving the interconversion of the PCMs between the resonant-bonded crystalline states and the covalent-bonded amorphous states is achieved through precise thermal modulation. Drawing from the thermal properties, an innovative thermodynamic leaky integrate-and-firing (TLIF) neuron system is proposed. With the TLIF neuron system as the fundamental unit, a fully connected SNN is constructed to complete a classic deep learning task: the recognition of handwritten digit patterns. The simulation results reveal that the exemplary SNN can effectively recognize 10 numbers directly in the optical domain by employing the surrogate gradient algorithm. The theoretical verification of our architecture paves a whole new path for integrated photonic SNNs, with the potential to advance the field of neuromorphic photonic systems and enable more efficient spiking information processing.

A comparative study of FPGA and CGRA technologies in hardware acceleration for deep learning

With the rapid growth of deep neural networks, their increasing demand for computing resources poses significant challenges to resource-constrained edge devices. Field Programmable Gate Array (FPGA) and Coarse-Grained Reconfigurable Arrays (CGRA) have emerged as promising solutions due to their parallelism and energy efficiency advantages. This paper conducts a comprehensive comparative analysis of FPGA and CGRA for accelerating deep learning workloads. It begins by introducing convolutional neural network architecture and optimization techniques. Various dataflow strategies are discussed for memory access optimization. The paper then analyzes representative cases to clarify FPGA and CGRA architectural advantages, along with optimization techniques through different dataflow strategies. The comparison reveals that FPGA offers higher throughput with fine-grained programmability for flexible bit-level operations and dataflow control. In contrast, CGRA excels in energy efficiency and area consumption with coarse-grained custom processing units and optimized on-chip interconnection networks. Quantitative comparisons are provided for throughput, energy efficiency, and area occupation. These insights can serve as a reference for selecting the appropriate architecture when designing custom hardware accelerators for deep learning workloads.

Cross-Core Data Sharing for Energy-Efficient GPUs

Graphics Processing Units (GPUs) are the accelerator of choice in a variety of application domains because they can accelerate massively parallel workloads and can be easily programmed using general-purpose programming frameworks such as CUDA and OpenCL. Each Streaming Multiprocessor (SM) contains an L1 data cache (L1D) to exploit the locality in data accesses. L1D misses are costly for GPUs due to two reasons. First, L1D misses consume a lot of energy as they need to access the L2 cache (L2) via an on-chip network and the off-chip DRAM in case of L2 misses. Second, L1D misses impose performance overhead if the GPU does not have enough active warps to hide the long memory access latency. We observe that threads running on different SMs share 55% of the data they read from the memory. Unfortunately, as the L1Ds are in the non-coherent memory domain, each SM independently fetches data from the L2 or the off-chip memory into its L1D, even though the data may be currently available in the L1D of another SM. Our goal is to service L1D read misses via other SMs, as much as possible, to cut down costly accesses to the L2 or the off-chip DRAM. To this end, we propose a new data sharing mechanism, called Cross-Core Data Sharing (CCDS) . CCDS employs a predictor to estimate whether or not the required cache block exists in another SM. If the block is predicted to exist in another SM’s L1D, CCDS fetches the data from the L1D that contains the block. Our experiments on a suite of 26 workloads show that CCDS improves average energy and performance by 1.30 × and 1.20 ×, respectively, compared to the baseline GPU. Compared to the state-of-the-art data-sharing mechanism, CCDS improves average energy and performance by 1.37 × and 1.11 ×, respectively.

Design of Network-on-Chip-Based Restricted Coulomb Energy Neural Network Accelerator on FPGA Device.

Sensor applications in internet of things (IoT) systems, coupled with artificial intelligence (AI) technology, are becoming an increasingly significant part of modern life. For low-latency AI computation in IoT systems, there is a growing preference for edge-based computing over cloud-based alternatives. The restricted coulomb energy neural network (RCE-NN) is a machine learning algorithm well-suited for implementation on edge devices due to its simple learning and recognition scheme. In addition, because the RCE-NN generates neurons as needed, it is easy to adjust the network structure and learn additional data. Therefore, the RCE-NN can provide edge-based real-time processing for various sensor applications. However, previous RCE-NN accelerators have limited scalability when the number of neurons increases. In this paper, we propose a network-on-chip (NoC)-based RCE-NN accelerator and present the results of implementation on a field-programmable gate array (FPGA). NoC is an effective solution for managing massive interconnections. The proposed RCE-NN accelerator utilizes a hierarchical-star (H-star) topology, which efficiently handles a large number of neurons, along with routers specifically designed for the RCE-NN. These approaches result in only a slight decrease in the maximum operating frequency as the number of neurons increases. Consequently, the maximum operating frequency of the proposed RCE-NN accelerator with 512 neurons increased by 126.1% compared to a previous RCE-NN accelerator. This enhancement was verified with two datasets for gas and sign language recognition, achieving accelerations of up to 54.8% in learning time and up to 45.7% in recognition time. The NoC scheme of the proposed RCE-NN accelerator is an appropriate solution to ensure the scalability of the neural network while providing high-performance on-chip learning and recognition.

A tree-recursive partitioned multicast mechanism for NoC-based deep neural network accelerator

In chip multiprocessor systems (CMPs), Network on Chip (NoC) has been widely used due to its advantages of favorable reusability, high reliability, and low power consumption. Recently, using NoC platforms to accelerate deep neural networks (DNNs) has become a new trend. This design can enable the intermediate computation results of DNNs to be transmitted within the chip, reducing the number of accesses to off-chip memory. However, a large amount of one-to-many traffic in the DNN accelerator will occupy the system bandwidth, which will significantly reduce the performance of the NoC platform dominated by one-to-one traffic. To address this issue, we propose a tree-based recursive partitioning multicast scheme (TRPM), which increases the path diversity and improves the system bandwidth. We also design a single-cycle per-hop router architecture, which effectively enhances the transmission efficiency of multicast packets. Detailed simulation results show that compared with the latest tree-based multicast algorithm for DNN accelerators, our scheme reduces the number of routed packets by 35%, the classification latency by 13.5% and the average packet latency by 14.5% on average.

IWO-IGA—A Hybrid Whale Optimization Algorithm Featuring Improved Genetic Characteristics for Mapping Real-Time Applications onto 2D Network on Chip

Network on Chip (NoC) has emerged as a potential substitute for the communication model in modern computer systems with extensive integration. Among the numerous design challenges, application mapping on the NoC system poses one of the most complex and demanding optimization problems. In this research, we propose a hybrid improved whale optimization algorithm with enhanced genetic properties (IWOA-IGA) to optimally map real-time applications onto the 2D NoC Platform. The IWOA-IGA is a novel approach combining an improved whale optimization algorithm with the ability of a refined genetic algorithm to optimally map application tasks. A comprehensive comparison is performed between the proposed method and other state-of-the-art algorithms through rigorous analysis. The evaluation consists of real-time applications, benchmarks, and a collection of arbitrarily scaled and procedurally generated large-task graphs. The proposed IWOA-IGA indicates an average improvement in power reduction, improved energy consumption, and latency over state-of-the-art algorithms. Performance based on the Convergence Factor, which assesses the algorithm’s efficiency in achieving better convergence after running for a specific number of iterations over other efficiently developed techniques, is introduced in this research work. These results demonstrate the algorithm’s superior convergence performance when applied to real-world and synthetic task graphs. Our research findings spotlight the superior performance of hybrid improved whale optimization integrated with enhanced GA features, emphasizing its potential for application mapping in NoC-based systems.

Design of fault tolerant algorithm for network on chip router using field programmable gate array

<p class="Abstract">Many internet protocol (IP) modules are present in contemporary system on chips (SoCs). This could provide an issue with interconnection among different IP modules, which would limit the system's ability to scale. Traditional bus-based SoC architectures have a connectivity bottleneck, and network on chip (NoC) has evolved as an embedded switching network to address this issue. The interconnections between various cores or IP modules on a chip have a significant impact on communication and chip performance in terms of power, area latency and throughput. Also, designing a reliable fault tolerant NoC became a significant concern. In fault tolerant NoC it becomes critical to identify faulty node and dynamically reroute the packets keeping minimum latency. This study provides an insight into a domain of NoC, with intention of understanding fault tolerant approach based on the XY routing algorithm for 4×4 mesh architecture. The fault tolerant NoC design is synthesized on Field programmable gate array (FPGA).</p>

Optimization of layout for embedding half hypercube into conventional tree architectures

SummaryEmbedding a graph into another graph can be utilized for structural simulation, processor allocation, and algorithm porting in the field of parallel architecture. This has the potential to enhance the physical layout of network‐on‐chip (NoC) devices as well as to investigate their virtualization possibilities. Layout is one of the many indicators of graph embedding. An optimal layout in NoC design can result in a decreased wiring area and cost, as well as the reduction in communication delay between parallel processing components. In this work, the guest graph is the half hypercube, which possess efficient routing, fault tolerance, and Hamiltonian features. The edge isoperimetric problems is solved for the half hypercube using a novel technique called the isochronal ordering. The host graphs considered in our work are complete binary trees, ‐rooted complete binary trees, and other few predominantly investigated tree based architectures.

PaCHNOC: Packet and Circuit Hybrid Switching NoC for Real-Time Parallel Stream Signal Processing.

Real-time heterogeneous parallel embedded digital signal processor (DSP) systems process multiple data streams in parallel in a stringent time interval. This type of system on chip (SoC) requires the network on chip (NoC) to establish multiple symbiotic parallel data transmission paths with ultra-low transmission latency in real time. Our early NoC research PCCNOC meets this need. The PCCNOC uses packet routing to establish and lock a transmission circuit, so that PCCNOC is perfectly suitable for ultra-low latency and high-bandwidth transmission of long data packets. However, a parallel multi-data stream DSP system also needs to transmit roughly the same number of short data packets for job configuration and job execution status reports. While transferring short data packets, the link establishment routing delay of short data packets becomes relatively obvious. Our further research, thus, introduced PaCHNOC, a hybrid NoC in which long data packets are transmitted through a circuit established and locked by routing, and short data packets are attached to the routing packet and the transmission is completed during the routing process, thus avoiding the PCCNOC setup delay. Simulation shows that PaCHNOC performs well in supporting real-time heterogeneous parallel embedded DSP systems and achieves overall latency reduction 65% compared with related works. Finally, we used PaCHNOC in the baseband subsystem of a real 5G base station, which proved that our research is the best NoC for baseband subsystem of 5G base stations, which reduce 31% comprehensive latency in comparison to related works.

Benchmarking Artificial Neural Network Architectures for High-Performance Spiking Neural Networks.

Organizations managing high-performance computing systems face a multitude of challenges, including overarching concerns such as overall energy consumption, microprocessor clock frequency limitations, and the escalating costs associated with chip production. Evidently, processor speeds have plateaued over the last decade, persisting within the range of 2 GHz to 5 GHz. Scholars assert that brain-inspired computing holds substantial promise for mitigating these challenges. The spiking neural network (SNN) particularly stands out for its commendable power efficiency when juxtaposed with conventional design paradigms. Nevertheless, our scrutiny has brought to light several pivotal challenges impeding the seamless implementation of large-scale neural networks (NNs) on silicon. These challenges encompass the absence of automated tools, the need for multifaceted domain expertise, and the inadequacy of existing algorithms to efficiently partition and place extensive SNN computations onto hardware infrastructure. In this paper, we posit the development of an automated tool flow capable of transmuting any NN into an SNN. This undertaking involves the creation of a novel graph-partitioning algorithm designed to strategically place SNNs on a network-on-chip (NoC), thereby paving the way for future energy-efficient and high-performance computing paradigms. The presented methodology showcases its effectiveness by successfully transforming ANN architectures into SNNs with a marginal average error penalty of merely 2.65%. The proposed graph-partitioning algorithm enables a 14.22% decrease in inter-synaptic communication and an 87.58% reduction in intra-synaptic communication, on average, underscoring the effectiveness of the proposed algorithm in optimizing NN communication pathways. Compared to a baseline graph-partitioning algorithm, the proposed approach exhibits an average decrease of 79.74% in latency and a 14.67% reduction in energy consumption. Using existing NoC tools, the energy-latency product of SNN architectures is, on average, 82.71% lower than that of the baseline architectures.

TROP: TRust-aware OPportunistic Routing in NoC with Hardware Trojans

Multiple software and hardware intellectual property (IP) components are combined on a single chip to form Multi-Processor Systems-on-Chips (MPSoCs). Due to the rigid time-to-market constraints, some of the IPs are from outsourced third parties. Due to the supply-chain management of IP blocks being handled by unreliable third-party vendors, security has grown as a crucial design concern in the MPSoC. These IPs may get exposed to certain unwanted practises like the insertion of malicious circuits called Hardware Trojan (HT) leading to security threats and attacks, including sensitive data leakage or integrity violations. A Network-on-Chip (NoC) connects various units of an MPSoC. Since it serves as the interface between various units in an MPSoC, it has complete access to all the data flowing through the system. This makes NoC security a paramount design issue. Our research focuses on a threat model where the NoC is infiltrated by multiple HTs that can corrupt packets. Data integrity verified at the destination’s network interface (NI) triggers re-transmissions of packets if the verification results in an error. In this article, we propose an opportunistic trust-aware routing strategy that efficiently avoids HT while ensuring that the packets arrive at their destination unaltered. Experimental results demonstrate the successful movement of packets through opportunistically selected neighbours along a trust-aware path free from the HT effect. We also observe a significant reduction in the rate of packet re-transmissions and latency at the expense of incurring minimum area and power overhead.

An efficient adaptive reconfigurable routing protocol for optimized data packet distribution in network on chips

The deadlock-free and live lock-free routing at the same time is minimized in the network on chip (NoC) using the proposed adoptive reconfigurable routing protocol (ARRP). Congestion condition emergencies are avoided using the proposed algorithm. The input packet distribution process is improved among all its shortest paths of output points. The performance analysis has been initiated by considering different configuration (N*N) mesh networks, by sending various ranges of data packets to the network on chip. The average and maximum power dissipation of XY, odd-even, Dy-XY algorithm, and proposed algorithm are determined. In this paper, an analysis of gate utilization during data packet transfer in various mesh configurations is carried out. The number of cycles required for each message injection in different mesh configurations is analyzed. The proposed routing algorithm is implemented and compared with conventional algorithms. The simulation has been carried out using reconfigurable two-dimensional mesh for the NoC. The proposed algorithm has been implemented considering array size, the routing operating frequency, link width length, value of probability, and traffic types. The proposed ARRP algorithm reduces the average latency, avoids routing congestion, and is more feasible for NoC compared to conventional methods.

A Metastability Risk Prediction and Mitigation Technique for Clock-Domain Crossing With Single-Stage Synchronizer in Near-Threshold-Voltage Multivoltage/ Frequency-Domain Network-on-Chip

For a network-on-chip (NoC) with multiple voltage/frequency domains, metastability hurts the reliability during the clock-domain crossing, especially in the near-threshold-voltage (NTV) region. Conventional multistage synchronizers reduce the probability of metastability but have a high latency penalty. This article presents a technique titled metastability risk prediction and mitigation (MPAM) that predicts the near-future metastability risks by a triple-phase clock monitoring circuitry and mitigates them by a metastability-free clock scheme. Therefore, the MPAM enables only one flip-flop for data synchronization without degrading the reliability against metastability, thus improving the latency and throughput of NoC. We prototyped a 2-by-2 NoC test chip with four independent voltage/frequency domains in a 40-nm low-power (LP) process, featuring the MPAM technique. The measurement shows that the MPAM significantly reduces the metastability condition rate by 10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{10}$</tex-math> </inline-formula> times under different clock frequency ratios. Moreover, by enabling only one flip-flop for synchronization, the MPAM-based NoC achieves packet latency reduction, throughput improvement, and energy efficiency gain by 58%, 13.4%, and 8.6%, respectively.

Fault protection of quasi-delay-insensitive pipeline models using efficient coding for asynchronous network-on-chip

&lt;div align="center"&gt;&lt;span&gt;One promising approach for creating the chip-level connection of multiprocessing system on chip (MPSoC) is asynchronous logic. However, asynchronous systems are susceptible to errors. In this manuscript, the efficient fault-tolerant (FT) quasi-delay-insensitive (QDI) pipeline modules are designed using a delay-insensitive redundant check (DIRC) coding mechanism. The DIRC coding approach can tolerate single and multi-bit transient faults (TFs) in QDI-pipeline modules. The 4-phase 1-of-n coding approach incorporates DIRC-based QDI pipeline stages to strengthen the asynchronous links against TFs. The DIRC-based QDI pipeline stages are further used as asynchronous links in asynchronous network-on-chip ((NoC) for fault-free communication. The performance metrics like chip area, delay, and power parameters are evaluated in detail against different data widths for both basic unprotected and DIRC-based QDI pipeline modules. &lt;br /&gt; The DIRC-based QDI-pipeline module with 1-of-4 code uses only &amp;lt;2% chip area with a delay of 7.4 ns and power of 117 mW on Artix-7 chip for data width 128. The code rate of the proposed work decreased by 33.33% for both 1-of-2 and 1-of-4 codes in DIRC-based QDI-pipeline modules.&lt;/span&gt;&lt;/div&gt;

Experimental demonstration of a nanobeam Fano laser.

Microscopic single-mode lasers with low power consumption, large modulation bandwidth, and ultra-narrow linewidth are essential for numerous applications, such as on-chip photonic networks. A recently demonstrated microlaser using an optical Fano resonance between a discrete mode and a continuum of modes to form one of the mirrors, i.e., the so-called Fano laser, holds great promise for meeting these requirements. Here, we suggest and experimentally demonstrate what we believe is a new configuration of the Fano laser based on a nanobeam geometry. Compared to the conventional two-dimensional photonic crystal geometry, the nanobeam structure makes it easier to engineer the phase-matching condition that facilitates the realization of a bound-state-in-the-continuum (BIC). We investigate the laser threshold in two scenarios based on the new nanobeam geometry. In the first, classical case, the gain is spatially located in the part of the cavity that supports a continuum of modes. In the second case, instead, the gain is located in the region that supports a discrete mode. We find that the laser threshold for the second case can be significantly reduced compared to the conventional Fano laser. These results pave the way for the practical realization of high-performance microlasers.

Comparative analysis of 2D mesh topologies with additional communication links for on-chip networks

Multiprocessor system-on-chip (MPSoC) is playing a vital role in recent embedded technologies. One of the main challenges of this system is its communication bottleneck which limits performance scaling capabilities. In order to overcome this restriction, on-chip interconnection networks have been proposed. Several topologies have been suggested in the literature, but the most popular one remains the mesh topology due to its systematic and scalable design structure. Although, the functionality and performance of network-based mesh topologies degrade significantly with growing system size, which results in the network diameter and the dependency on small bisection width. A wide range of modified designs has been proposed in the literature with various types of additional links to improve the network performance. However, these links result in additional cost overhead on the system in terms of area, energy, and power consumption. Among the selected competitor meshes, it is observed that the link design of d-Torus produces high performance at elevated communication costs. The design of the CBP-Torus is less complex and results in lower communication costs compared to d-Torus with similar performance. The selection of an appropriate mesh-type topology of the target application is, therefore, a tradeoff between the performance and cost of the network. This paper analyzes the impact of additional links on the performance of on-chip mesh architectures. The comparative analysis includes performance characteristics, structural complexity, power consumption, and area utilization. This research work provides a roadmap for the designers to choose the most appropriate topology for a particular design.

Routing Techniques in Network-On-Chip Based Multiprocessor-System-on-Chip for IOT: A Systematic Review

Routing techniques (RTs) play a critical role in modern computing systems that use network-on-chip (NoC) communication infrastructure within multiprocessor system-on-chip (MPSoC) platforms. RTs contribute greatly to the successful performance of NoC-based MPSoCs due to traffic congestion avoidance, quality-of-service assurance, fault handling and optimisation of power usage. This paper outlines our efforts to catalogue RTs, limitations, recommendations and key challenges associated with these RTs used in NoC-based MPSoC systems for the IoT domain. We utilized the PRISMA method to collect data from credible resources, including IEEE Xplore ®, ScienceDirect, Association for Computing Machinery and Web of Science. Out of the 906 research papers reviewed, only 51 were considered relevant to the investigation on NoC RTs. The study addresses issues related to NoC routing and suggests new approaches for in-package data negotiating. In addition, it gives an overview of the recent research on routing strategies and numerous algorithms that can be used for NoC-based MPSoCs. The literature analysis addresses current obstacles and delineates potential future avenues, recommendations, and challenges analyzing techniques to assess performance utilizing metrics within the TCCM framework.

AS-Router: A novel allocation service for efficient Network-on-Chip

Assigning input ports to output ports and allowing flits to pass through the switch without colliding is accomplished by Switch Allocation (SA), a crucial pipeline stage in the Network-on-Chip (NoC) router. Earlier research improved the efficiency of matching to enhance SA processes. The studies in question, however, failed to account for the importance of information sharing between the various phases of the router’s pipeline. To improve NoC routers’ allocation, this article introduces the Allocation Service (AS) concept. By adding a new pipeline stage called Request Finalization (RF) before the SA stage, the AS can be optimized. The RF stage’s objective is to complete the uniform request and Endpoint Congestion Causing (EPC) requests for SA before sending them on their way. These results inform the proposal of a new design, the CUE-Router, to increase AS by the integration of an RF stage and inter-pipeline communication between routers. Two new types of router architecture form the basis for CUE-Router. The first thing we do in this work is introduce URR-Router, a router that only allocates EPC requests if there are no uniform requests in the SA stage, effectively giving uniform requests a priority. The second example is the EPR-Router, which alleviates endpoint congestion by favoring EPC requests over uniform ones. In this work, we take a fresh look at the SA process optimization that underpins the low-latency CUE-Router architecture by cycling through a series of prioritization changes between uniform requests and EPC requests. CUE-Router greatly improves SA efficiency and network performance by facilitating communication between the various stages of the pipeline. Based on the results of the analysis, our approach has the potential to significantly enhance performance with minimal additional effort.

Design analysis of moth-flame optimized fault tolerant technique for minimally buffered network-on-chip router

&lt;span&gt;A network on a chip is a solitary silicon chip utilized to perform the communication characteristics of large-scale (LSI) to very large-scale integration (VLSI) systems. Network-on-chip (NoC) architecture includes links, network interfaces (NI), and routers to unite with external memories or processors. NoC is designed to flow messages from the source module to the destination module through several links involving routing decisions. &lt;br /&gt; The design of NoC is complex and the buffer section’s expensiveness creates problems while providing secured data service. Moreover, routers and links in NoC setups are liable to faults. This work introduces a minimal buffered router, and the faults in the network are optimized using moth flame optimized (MFO) fault-tolerant technique. The software named Xilinx ISE design suite 14.5 is employed for the minimum buffered router model. &lt;br /&gt; The suggested scheme is operated with less area, low power (0.241 mW), and high speed (965.261 Megahertz (MHz)) when matched with previous works.&lt;/span&gt;