Abstract
The deadlock-free and live lock-free routing at the same time is minimized in the network on chip (NoC) using the proposed adoptive reconfigurable routing protocol (ARRP). Congestion condition emergencies are avoided using the proposed algorithm. The input packet distribution process is improved among all its shortest paths of output points. The performance analysis has been initiated by considering different configuration (N*N) mesh networks, by sending various ranges of data packets to the network on chip. The average and maximum power dissipation of XY, odd-even, Dy-XY algorithm, and proposed algorithm are determined. In this paper, an analysis of gate utilization during data packet transfer in various mesh configurations is carried out. The number of cycles required for each message injection in different mesh configurations is analyzed. The proposed routing algorithm is implemented and compared with conventional algorithms. The simulation has been carried out using reconfigurable two-dimensional mesh for the NoC. The proposed algorithm has been implemented considering array size, the routing operating frequency, link width length, value of probability, and traffic types. The proposed ARRP algorithm reduces the average latency, avoids routing congestion, and is more feasible for NoC compared to conventional methods.
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