Negative Gate Bias Research Articles

Channel Length-Dependent Charge Detrapping on Threshold Voltage Shift of Amorphous InGaZnO TFTs Under Dynamic Bias Stress

The demand for amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) has been increasing due to their high mobility and transparent properties. In this paper, we report on the channel length (L)-dependent charge detrapping phenomenon of a-IGZO TFTs by observing a threshold voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift under dynamic bias stress. Dynamic gate bias stresses are applied to the devices with three types of L: 25, 50, and 100 μm. The positive gate bias with different stress durations is followed by the negative gate bias. Under the sequential negative gate bias stress, the reversible shift of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> increases due to charge detrapping of the previously trapped charges. As L increases, the negative shift of Vth increases due to the decreased charge detrapping time and high electric field induced by a small subgap density of states.

Bias-Stress-Induced Instabilities in P-Type ${\rm Cu}_{2}{\rm O}$ Thin-Film Transistors

We investigate the gate bias-stress-induced instabilities of p-type copper oxide $({\rm Cu}_{2}{\rm O})$ thin-film transistors (TFTs). Transfer curves measured before and after the application of constant gate bias stress under air and vacuum environments show that the partial pressure of the oxygen in the environment does not much affect the transfer characteristics and bias-stress-induced instabilities of the ${\rm Cu}_{2}{\rm O}$ TFTs. During the negative gate bias stresses, the transfer curves shift to the negative direction without a significant variation of the shape, which is attributed to the hole trapping in the interface or bulk dielectric layers with a negligible creation of additional interface trap states. During the positive gate bias stresses, a threshold voltage hardly moves to the positive direction because of the lack of free electron inside the p-type ${\rm Cu}_{2}{\rm O}$ , but a notable degradation of the subthreshold slope is observed. From the recovery characteristics, the generated traps during the positive gate bias stress are estimated to be metastable ones in p-type ${\rm Cu}_{2}{\rm O}$ TFTs.

Kinetic Stress Testing and the Influence of Long-Time Anneals on the Behavior of IZO Thin Film Transistors

Stability testing of indium-zinc oxide under extreme conditions is necessary before the metal oxide can be deemed a reliable alternative to a-Si as channel layer in thin film transistors (TFTs). In this paper, we apply thermal stress under positive and negative gate bias stress creating practical application conditions. This stress scenario gives greater insight into thermally activated defects in the presence of an electrical field. Operational temperatures of 20 °C, 50 °C, and 80 °C are used, and a more rapid degradation of the devices is seen with increased temperatures. Kink and dip are observed due to the donor-like trapped charges increasing the subthreshold swing and acceptor-like trapped charges reducing the ON current, respectively. Post fabrication, long-time anneals for 12-, 24-, 36-, 48-, and 60-h at low temperatures (150 °C) are performed to alleviate defects. The 48-h annealed TFTs show remarkable stability under extreme temperatures and electric fields maintaining a high ON-OFF ratio (~108) after 104 s. This is attributed to the reduced density of charges in acceptor-like trap states, modeled to reduce by 58% from a 12-h anneal and to insignificant extent over a 48-h anneal.

Nonvolatile memory device based on SiO 2 /GaN/AlGaN/GaN heterostructure

Demonstrated is a nonvolatile memory device based on a SiO2/GaN/AlGaN/GaN heterostructure in which the upper GaN layer acted as a storage node. Charges were stored in and released from the upper GaN layer by applying positive and negative gate biases, respectively. The top SiO2 layer acted as a blocking layer. The threshold voltage shift was ∼ 3 V between the program and erase modes and the retention characteristics were very stable over 10000 s.

Single-Nanowire CMOS Inverter Based on Ambipolar Si Nanowire FETs

We have successfully fabricated an inverter based on ambipolar Si nanowire FETs. The inverter is consisted of two identical nanowire FETs on a single Si nanowire. The engaged FETs showed asymmetric ambipolar characteristics under positive and negative gate bias. A CMOS-like inverter can be realized on the single nanowire, where one of the devices behaves as an nMOSFET and the other behaves as a pMOSFET.

Measurement and Identification of Three Contributing Charge Terms in Negative Bias Temperature Instability

The increase in the magnitude of the threshold voltage of a positive-channel metal oxide semiconductor (PMOS) under negative gate biasing (negative bias temperature instability) is attributed to the build-up of charge in the gate insulator. We have studied the charging and discharging of nitrided SiO2 gate insulator field effect transistors and through the use of pseudo-DC and pulsed stressing methods, have extracted, at least, three charging components. These components are (a) the charging of interface states at the semiconductor/insulator boundary, (b) dynamically recoverable positive charging in the "bulk" of the insulator, and (c) positive charging in the insulator, which can be "eliminated" only by application of a positive electric field across the insulator. It is proposed that the charge "elimination" in (c) arises via a charge neutralization process involving electron capture at switching traps, as opposed to de-trapping, and that this can be reversed by the application of a small negative field.

(Invited) Instability Assessment and Modeling Of Amorphous InGaZnO Thin Film Transistors Under Alternating Pulse Bias Stresses

Amorphous InGaZnO (a-IGZO) TFTs have attracted more demands due to the transparency and high mobility. Since TFTs are always exposed to both positive and negative gate bias, the alternating DC bias stress tests are required to ensure stable TFT characteristics. Moreover, the analysis about scaling-down behavior under bias stress condition is required. In this paper, the effects of alternating pulse bias stress on the threshold voltage shift (ΔVth) of a-IGZO TFTs with respect to the stress time duration (t d) are analyzed by the variation of interface trap charges (Qit) and the channel electric field (E-field). In addition, the channel length-dependent tendency is verified using the concepts of the subgap density of states (DOS) and density of total trap states (NT).

Electronic properties of light-emitting p-n hetero-junction array consisting of p+-Si and aligned n-ZnO nanowires

Hetero-junction array of p+-Si/n-ZnO nanowires (NWs) was fabricated via contacting of aligned ZnO NWs onto a patterned p+-Si substrate. Current-voltage (I-V) measurement on the p-n junction showed a rectification behavior with a high rectification ratio of 104 at ±3 V. In addition, the enhancement of forward current as well as the decrease of the turn-on voltage was observed with the application of negative gate bias and noticeable p-type gate dependence, which was explained in terms of asymmetric shift of the Fermi levels with gate bias in the suggested energy band diagram. Such formed hetero-junction devices showed strong UV sensitivity of 2 × 104 under reverse bias of −3 V and electroluminescence in both UV and visible ranges, suggesting its potential applicability in optoelectronic devices.

Negative gate-bias temperature stability of N-doped InGaZnO active-layer thin-film transistors

Stability of negative bias temperature stress (NBTS) of nitrogen doped amorphous InGaZnO (a-IGZO) thin-film transistor (TFT) is investigated. Undoped a-IGZO TFT stressed at 333 K exhibit a larger negative ΔVTH (−3.21 V) with an unpredictable sub-threshold swing (SS) of hump shaped transfer curve due to the creation of meta-stable traps. Defects related hump formation has disappeared with small ΔVTH (−1.13 V) and ΔSS (0.018 V/dec) in nitrogen doped a-IGZO TFT. It is observed that nitrogen doping enhances device stability by well controlled oxygen vacancy and trap sites in channel and channel/dielectric interface.

Nitric acid compensated aluminum oxide dielectrics with improved negative bias reliability and positive bias temperature response

The room-temperature nitric acid (HNO3) compensation method is introduced to effectively improve the dielectric quality of ultrathin aluminum oxide (Al2O3) gate dielectrics under low thermal budget consideration. The physical properties, electrical characteristics, and temperature response of Al2O3 metal-oxide-semiconductor (MOS) devices without and with HNO3 compensation are compared. The surface roughness and interface trap density are obviously decreased by utilizing HNO3 compensation. Under negative gate bias, the leakage current, hard breakdown characteristics, and temperature-dependent reliability of the Al2O3 MOS(p) capacitors are clearly improved by HNO3 compensation. Under positive gate bias, the highly temperature-dependent current is principally dominated by generation-recombination mechanism. However, the diodes without HNO3 compensation show irregular temperature response especially at temperature above 70 °C. From Frenkel-Poole emission analysis, the oxide traps in Al2O3 without HNO3 compensation are responsible to this abnormal temperature response. These results suggest that the quality of ultrathin Al2O3 gate dielectrics can be cost-effectively improved by HNO3 compensation.

Drain bias effect on the instability of amorphous indium gallium zinc oxide thin film transistor

We fabricated amorphous indium gallium zinc oxide thin film transistors (TFTs) in a top gate structure on a glass substrate. We investigated the effect of drain bias on the instability of the device. Although the device showed highly stable characteristics under both positive and negative gate bias stress, it showed significant degradation in the transfer characteristics under drain bias stress. The degradation phenomena are somewhat similar to those of negative gate bias illumination stress (NBIS). In the case of NBIS, degradation mechanisms have been confused between two kinds of illustrations, one of which is hole trapping in the gate insulator and the other is an increase of electron density in the active layer. Our experimental results revealed that the degradation mechanism of drain bias stress is closer to the latter mechanism of NBIS in amorphous oxide TFTs.

Comparison of CuPc-based organic thin-film transistors made by different dielectric structures

Copper phthalocyanine-based organic thin-film transistors (OTFTs) with gate dielectric made by different combinations of ZrO2 and Al2O3 are fabricated. Experimental results show that as compared to the OTFTs with ZrO2/Al2O3 stacked and Al2O3/ZrO2/Al2O3 sandwiched gate dielectric, the device fabricated with the Al2O3/ZrO2 stacked gate dielectric manifests better electrical properties such as larger on/off ratio, smaller subthreshold slope, and higher carrier mobility. This could be explained by the fact that Al2O3 has good interface properties with CuPc and can act as a barrier layer, which prevents intermixing of materials at the organic/insulator interface and can slow oxygen diffusion through Al-O matrix, thus suppressing interfacial trap density. The gate-bias stress effect on the performance of OTFTs is also investigated. It is found that the threshold voltage shifts toward positive direction with stress time under a negative gate bias voltage. Longer stress times cause more degradation of the subthreshold and on/off ratio, probably due to more defect-state creation in the channel and an increase of interfacial traps and oxide charges in the dielectric during stress. Results also indicate that OTFTs with Al2O3 interlayer between the high-k dielectric and the gate electrode have less degradation in subthreshold and on/off ratio after a 3600-s stress. The involved mechanism lies in that the Al2O3 interlayer at the high-k dielectric/gate electrode interface can effectively block the injection of electrons from the gate electrode into the high-k material during electrical stress and thus less stress-induced interfacial traps and negative oxide charges in the devices. The electrical characteristics of the OTFTs after the removal of gate bias for a period of time are also studied.

Dependence of Light-Accelerated Instability on Bias and Environment in Amorphous Indium-Gallium-Zinc-Oxide Thin Film Transistors

This study examines the dependence of light-accelerated instability on bias and environment in amorphous indium-gallium-zinc-oxide thin film transistors. When device is in vacuum ambient, the threshold voltage of device after negative gate bias illumination stress (NBIS) showed bias-dependent electrical degradation behavior. However, experimental results show the degradation of electrical characteristic in a-IGZO devices does not only rely on the charge trapping mechanism for NBIS. During NBIS in oxygen, moisture-simulated and atmosphere ambient, the negative shift in electrical characteristic is suppressed when compared to that in vacuum. This implies that the adsorbent gas species in the surrounding environment dominates the electrical characteristic degradation of devices during NBIS, which leading the change of dominant mechanism from photon-created carrier trapping to adsorbed/desorbed gas phenomenon.

Design and Investigation of an Isolated Gate Driver Using CMOS Integrated Circuit and HF Transformer for Interleaved DC/DC Converter

This paper deals with the design and the implementation of an isolated gate driver system using a CMOS integrated circuit for interleaved dc/dc converters. It is based on a novel gate driver topology for power switches like MOSFETs and insulated-gate bipolar transistors. Composed of two legs of a CMOS inverter, a high-frequency pulse transformer, and two Zener diodes connected in antiseries configuration with the gate of the power switch, this driver topology provides an optimal bipolar gate driver waveform with greater positive and negative gate biases to fasten the switch on and off. It represents a simple ultracompact isolated gate driver simple to integrate in CMOS technology. Power consumption, system size, and robustness of the gate driver are therefore optimized. This integrated driver circuit can be used for any multitransistor applications. We detail the operation principle of the proposed driver topology in this paper. We implemented the gate driver to control a three-phase interleaved boost converter; the results show the effectiveness of the proposed driver system.

Current conduction and stability of CeO2/La2O3 stacked gate dielectric

The current conduction behaviors in CeO2/La2O3 stack are studied. We found that large amount of hole injection under large negative gate bias can give rise to the accumulation of neutral interstitial oxygen (OI) species which serve as acceptors and promotes the hole conduction in the La2O3 film. Whereas if the amount of hole injection is lower than that of the oxygen anions injected from the capping CeO2 layer under a sufficient large negative gate bias, the amount of OI reduces and a negative charge built-up results which further reduces the leakage current and threshold voltage of p-channel metal-oxide-semiconductor transistors.

Electrical and optical properties of light-emitting field-effect transistors based on MEH-PPV polymer composite films with ZnO nanoparticles

The optical and electrical properties of light-emitting field-effect transistor structures with an active layer based on nanocomposite films containing zinc oxide (ZnO) nanoparticles dispersed in the matrix of the soluble conjugated polymer MEH-PPV have been investigated. It has been found that the current-voltage characteristics of the field-effect transistor based on MEH-PPV: ZnO films with a composite component ratio of 2: 1 have an ambipolar character, and the mobilities of electrons and holes in these structures at a temperature of 300 K reach high values up to ∼1.2 and ∼1.4 cm2/V s, respectively, which are close to the mobilities in fieldeffect transistors based on ZnO films. It has been shown that the ambipolar field-effect transistor based on MEH-PPV: ZnO films emits light at both positive and negative gate bias voltages. The mechanisms of injection, charge carrier transport, and radiative recombination in the studied structures have been discussed.

The suppressed negative bias illumination-induced instability in In-Ga-Zn–O thin film transistors with fringe field structure

This study investigates the suppressed negative gate bias illumination stress (NBIS) -induced instability of via-type amorphous indium-gallium-zinc-oxide (a-IGZO) thin film transistors (TFTs) with fringe field (FF) structures. The less negative threshold voltage shifts of devices after NBIS are showed when device has larger FF structures. This finding is attributed to more dispersive distribution of photo-generated holes in the width direction of a-IGZO during NBIS, which reduce the hole trapping phenomenon in the front channel interface. The a-IGZO TFT with FF structure is expected to be an effective method to increase the electrical reliability of devices after NBIS.

Ambipolar field-effect transistors with bilayered thiophene/phenylene co-oligomers

Bilayered organic field-effect transistors were fabricated by successive vapor-depositions of 1,4-bis{5-[4-(trifluoromethyl)phenyl]thiophene-2-yl}benzene (AC5-CF3) and 5,5″-bis(4-biphenylyl)-2,2′:5′,2″-terthiophene (BP3T). With decreasing thickness of the n-type AC5-CF3 film in contact with the dielectric layer, ambipolar characteristics were improved under both positive and negative gate biases. Two types of asymmetric source/drain electrodes were prepared by either obliquely shadowed lamination or mask-shifted depositions of AlLi and Au. The latter method in which the device was characterized without exposure to air after the electrode deposition of AlLi resulted in remarkable improvement of ambipolarity and reduction of leak currents. Finally, optimized ambipolar mobilities of μe=5.00×10−2 and μh=1.56×10−2cm2V−1s−1) were obtained with 5-nm-thick AC5-CF3 and 30-nm-thick BP3T.

Effect of the Electrode Materials on the Drain-Bias Stress Instabilities of In–Ga–Zn–O Thin-Film Transistors

The effects of electrode materials on the device stabilities of In-Ga-Zn-O (IGZO) thin-film transistors (TFTs) were investigated under gate- and/or drain-bias stress conditions. The fabricated IGZO TFTs with a top-gate bottom-contact structure exhibited very similar transfer characteristics between the devices using indium-tin oxide (ITO) and titanium electrodes. Typical values of the mobility and threshold voltage of each device were obtained as 13.4 cm(2) V(-1) s(-1) and 0.72 V (ITO device) and 13.8 cm(2) V(-1) s(-1) and 0.66 V (titanium device). Even though the stabilities examined under negative and positive gate-bias stresses showed no degradation for both devices, the instabilities caused by the drain-bias stress were significantly dependent on the types of electrode materials. The negative shifts of the threshold voltage for the ITO and titanium devices after the 10(4)-s-long drain-bias stress were estimated as 2.06 and 0.96 V, respectively. Superior characteristics of the device using titanium electrodes after a higher temperature annealing process were suggested to originate from the formation of a self-limiting barrier layer at interfaces by nanoscale observations using transmission electron microscopy.

Transparent Al–In–Zn–O Oxide semiconducting films with various in composition for thin-film transistor applications

Al–In–Zn–O thin-film transistors were fabricated. To examine the effect of In composition, we adopted a co-sputtering method using Al–Zn–O and In2O3 targets. The sputtering power of In2O3 was varied to 200, 150, and 50W. The mobility and turn-on voltage of each device were 27.8cm2V−1s−1 and −4.2V, 4.5cm2V−1s−1 and −3.5V, 0.7cm2V−1s−1 and −3V, respectively. We also investigated instabilities under negative gate bias stress (NBS) and negative bias illumination stress (NBIS). While the NBS was not influenced by the In contents, the NBIS characteristics were optimized for the device with In2O3 sputtering at 150W.