Measurement and Identification of Three Contributing Charge Terms in Negative Bias Temperature Instability

Abstract

The increase in the magnitude of the threshold voltage of a positive-channel metal oxide semiconductor (PMOS) under negative gate biasing (negative bias temperature instability) is attributed to the build-up of charge in the gate insulator. We have studied the charging and discharging of nitrided SiO2 gate insulator field effect transistors and through the use of pseudo-DC and pulsed stressing methods, have extracted, at least, three charging components. These components are (a) the charging of interface states at the semiconductor/insulator boundary, (b) dynamically recoverable positive charging in the "bulk" of the insulator, and (c) positive charging in the insulator, which can be "eliminated" only by application of a positive electric field across the insulator. It is proposed that the charge "elimination" in (c) arises via a charge neutralization process involving electron capture at switching traps, as opposed to de-trapping, and that this can be reversed by the application of a small negative field.