Negative Flatband Voltage Research Articles

Water-Related Hole Traps at Thermally Grown GeO2–Ge Interface

The generation mechanism of positive charge present in germanium oxide film thermally grown on a germanium substrate has been investigated in this study. Water-related hole traps are generated in the interfacial germanium suboxide layer. The negative flat-band voltage shift due to the charged hole traps increases with increasing electric stress field in the oxide. Both low-temperature growth of the oxide film and postmetallization annealing have been proposed for the improvement of the flat-band voltage shift. The former is effective in minimizing the suboxide layer thickness by suppressing germanium monoxide volatilization during the oxide growth. The latter method successfully reduces the density of traps caused by water desorption from the interfacial suboxide layer.

Anomalous positive flatband voltage shifts in metal gate stacks containing rare-earth oxide capping layers

It is shown that the well-known negative flatband voltage (VFB) shift, induced by rare-earth oxide capping in metal gate stacks, can be completely reversed in the absence of the silicon overlayer. Using TaN metal gates and Gd2O3-doped dielectric, we measure a ∼350 mV negative shift with the Si overlayer present and a ∼110 mV positive shift with the Si overlayer removed. This effect is correlated to a positive change in the average electrostatic potential at the TaN/dielectric interface which originates from an interfacial dipole. The dipole is created by the replacement of interfacial oxygen atoms in the HfO2 lattice with nitrogen atoms from TaN.

Electrical and optical characteristics of porous silicon impregnated with LaF 3 by a novel chemical bath technique

The structural, electrical and optical characteristics of porous silicon (PS) due to the impregnation of LaF 3 into PS by a novel chemical-bath deposition (CBD) technique have been investigated in this article. Without removing the PS from the anodization chamber the impregnation with LaF 3 has been done by reacting LaCl 3 with HF in the same chamber at room temperature. The impregnation of LaF 3 was confirmed by the SEM on the cross-section of the LaF 3/PS/Si system and EDX. The modification of PS surface by LaF 3 had direct influence on the electrical and optical properties of PS. Electrical properties of Ag/LaF 3/PS/p-Si/Ag structures were studied through the current–voltage ( I– V) and capacitance–voltage ( C–V) characteristics. Formation of metal–insulator–semiconductor (MIS) diode was evident whose forward current increased with annealing. A diode factor of about 2.4 has been obtained for the annealed heterostructure indicating a high density of trap states. The C −2- V curves of all samples showed negative flat band voltage of around −2 V confirming a large number of fixed positive charges in the LaF 3. The photoluminescence (PL) intensity of the LaF 3-impregnated PS showed aging for the as-deposited samples, but when annealed PS structure recovered the PL intensity. Experimental results show that the optimized chemical bath passivation process for the LaF 3 on porous silicon could enable the porous silicon to be an important material for photonic application.

High temperature (1000 °C) compatible Y–La–Si–O silicate gate dielectric in direct contact with Si with 7.7 Å equivalent oxide thickness

Yttrium lanthanum silicate was formed in direct contact with silicon after a rapid thermal annealing at 1000 °C in metal-oxide-semiconductor capacitors leading to an equivalent oxide thickness (EOT) of 7.7 Å. This represents one of the lowest EOT value reported for a gate-first process with non Hf-based dielectric. The silicate is formed by interdiffusion of La2O3 and YOx layers and interfacial SiO2 consumption. Yttrium incorporation reduces the leakage current density as well as the large negative flatband voltage (Vfb) shift that is associated with lanthanide-based dielectrics. The Vfb value can be appropriately tuned for n-type field-effect transistor operation by changing the silicate composition.

Effects of Structural Transformation of Metal-GeO2 Interface on Electrical Properties

The relations between physical structural transformations and improvement of electrical properties of metal/GeO2/Ge systems using low temperature oxidation and the post metal deposition annealing (PDA) have been investigated. In metal/GeO2/Ge systems, we found that the electrical properties were drastically improved by the oxidation and the PDA. The oxidation at low temperature achieves no C-V hysteresis because of suppression of GeO desorption. on the other hand, according to results of X-ray photoelectron spectroscopy (XPS) and thermal desorption spectroscopy (TDS), the improvement mechanism of electrical properties of metal/GeO2/Ge structures after the PDA was clearly shown as follows. Once the metals were deposited on the GeO2, GeOx layer was formed at the surface region of the GeO2 due to reduction of the oxide by the metals. The sub-oxide layer at the interface causes a large negative flat-band voltage (VFB) shift on the capacitance-voltage (C-V) characteristics of the metal/GeO2/Ge structures. Then, during the PDA process at low temperature, the sub-oxide layer is disappeared with desorbing as germanium monoxide (GeO) gas, and the VFB shifts of the metal/GeO2/Ge systems were drastically improved and also their accumulation capacitances were increased because of disappearance of the sub-oxide layer.

Effect of post-deposition annealing temperature on CeO 2 thin film deposited on silicon substrate via RF magnetron sputtering technique

Physical and electrical properties of CeO 2 thin film deposited on p-type silicon substrate via the RF magnetron sputtering technique after treating in argon ambient at different annealing temperatures has been investigated and reported. Thickness of the CeO 2 thin film was in the range of 30–40 nm measured by an ellipsometer at 5 different points for each sample. Post-deposition annealing was executed in argon ambient for 30 min at four different temperatures (400, 600, 800, and 1000 °C). The physical results demonstrated that the thin film was free of physical defects and root-mean square surface roughness decreased as the annealing temperature increased. X-ray diffraction indicated the occurrence of CeO 2 phase with four diffraction planes [(1 1 1), (2 0 0), (2 2 0), and (3 1 1)]. All samples showed negative flat band voltage shift owing to the existence of positive effective oxide charges. Samples annealed at 1000 °C showed the lowest interface trap density, total interface trap density, effective oxide charge, and the highest barrier height. This attributed to the lowest leakage current density (∼1×10 −9 A cm −2) and the highest electric breakdown voltage (∼30 V) of the sample when a comparison was made.

Effects of La2O3 Capping Layers Prepared by Different ALD Lanthanum Precursors on Flatband Voltage Tuning and EOT Scaling in TiN/HfO2/SiO2/Si MOS Structures

The use of thin capping layers that are inserted between the gate metal and dielectric layers have been shown to simultaneously cause a negative flatband voltage (Vfb) shift and to stabilize low threshold voltage (VTH). A major challenge with capping layers is to achieve adequate effective work function shifts without large increases in equivalent oxide thickness (EOT) (ΔEOT). In this work, the effects of La2O3 cap layers prepared by different ALD Lanthanum precursors, La(fAMD)3 and La(thd)3, on flatband voltage tuning and EOT scaling in TiN/HfO2/SiO2/Si metal oxide semiconductor (MOS) structures was investigated. Experimental results showed that ΔVfb and ΔEOT as high as 0.45 V and 0.055 nm, caused by dipoles at the lower interface between HfO2 and SiO2 interlayer and the diffusion of La and Hf atoms to the SiO2 interlayer, were achieved by a 1 nm thick La2O3 capping layer using a La(fAMD)3 precursor, while a relatively smaller Vfb and EOT of −0.7 V and 1.27 nm were obtained from the noncap TiN/HfO2/SiO2/Si MOSCAP sample. The use of a La(fAMD)3 precursor for the La2O3 capping layer deposition has been shown being much superior to La(thd)3 due to lower atomic layer deposition (ALD) process temperature and shorter O3 oxidant pulse duration.

Epitaxial SrO interfacial layers for HfO2–Si gate stack scaling

We discuss the structural and electrical properties of scaled 2 nm HfO2/SrO gate stacks. Thin SrO layers are deposited by molecular beam epitaxy onto (001) p-Si substrates as alternative passivating interfacial layers (ILs) to SiO2. X-ray photoelectron spectroscopy and transmission electron microscopy show that, despite some HfO2–SrO intermixing, the SrO IL acts as a barrier against HfxSiy and SiO2 formation during high-κ deposition. Electrical measurements on metal-oxide-semiconductor capacitors with TiN metal gates integrated in a low-temperature process flow reveal an equivalent oxide thickness of 5 Å with competitive leakage current and hysteresis and a negative flat band voltage shift, suitable for n-channel transistors.

Scaling equivalent oxide thickness with flat band voltage (VFB) modulation using in situ Ti and Hf interposed in a metal/high-k gate stack

This study aimed to control the work-functions and scaling equivalent oxide thicknesses (EOTs) of metal-oxide-semiconductor (MOS) devices using an “in situ” thin metal layer interposed between the gate dielectric and the metal gate. The effects of “in situ thin metal layers” were imposed to suppress low-k interfacial oxide formation, leading to a thin EOT (down to 0.5 nm) scaling due to the scavenging of excess oxygen sources through gate stacks and to allow for the tuning of nMOS and pMOS-compatible work-functions using Hf and Ti layers, respectively. Different high-k gate dielectrics (HfO2, HfOxNy), two types of transition metals (Ti, Hf), and various annealing temperature conditions were studied. The EOT became thinner as the thicknesses of the Hf and Ti thin layers increased. However, the thickening Hf cap provided a negative flat band voltage (VFB) shift, while the increasing Ti exhibited a positive VFB shift.

Optimization of Poly-silicon Process for 3C-SiC Based MOS Devices

AbstractCubic 3C-SiC is regarded as a perfect material for medium power MOSFETs with blocking voltages of around 1500V and current handling of 100A and more. One of the main issues to realize such power MOSFETs is the improvement of the MOS gate to ensure low on-state resistance operation.The benefits of the implementation of an advanced oxidation process combining PECVD SiO2 deposition and short post-oxidation steps in wet oxygen has been previously demonstrated [1]. The concentrations of fixed and mobile charges in the oxide and at the SiO2/SiC interface were significantly reduced. But the optimization of the gate material is still an issue.The experiences from silicon technology point in the direction of using a poly-Si gate for MOS controlled devices. Significant improvements in terms of gate oxide reliability could be achieved by applying a poly-Si gate. But the usage of hydrogen for passivation of defects in oxides grown on 3C-SiC gives restrictions to the poly-Si deposition and activation process conditions. A reduced thermal budget is required to preserve the high electrical properties of the oxide.We investigated the electrical properties of MOS structures prepared with poly-Si gates. The poly-Si layer was deposited by the LPCVD technique mixing Si2H6 and PH3 at 380°C. The poly-Si activation has been carried out with five different methods. The influence of the following two main parameters has been considered: the process duration (thermal annealing or rapid thermal annealing) and the gas atmosphere (argon, dry or wet oxygen).MOS capacitors were fabricated on the oxidized free-standing n-type 3C-SiC (001) wafers with 5μm low nitrogen doped (5×1015 cm-3) epitaxial layers. The MOS capacitors were characterized on the wafer level (about 200 MOS structures per wafer) by capacitance-conductance-voltage (C-G-V) measurements using a HP4284A LCR meter in the frequency range of 100 Hz to 1 MHz. The measurements were performed at room temperature in a light-tight and electrically shielded environment. The interface trap densities Dit were extracted by the conductance method. To assess the oxide reliability, time-zero dielectric breakdown (TZDB) measurements were conducted on the fabricated MOS structures.The optimized poly-Si activation process based on RTA in argon has minimal thermal budget and preserves the oxide and interface quality. The fabricated MOS structures demonstrate high electrical properties and reliability of the oxide: A small negative flat band voltage shift of -1V and an interface state density Dit of 7.4×1010 eV-1cm-2 at 0.63 eV below the conduction band. The TZDB measurements revealed an average breakdown electric field of 9.4 MV/cm.

Characterization upon potential properties of HfO2 stabilized by Y2O3 films as cubic phase

In this article, we have experimentally investigated the nanometer thick cubic HfO2 stabilized with 6 mol % Y2O3 (YSH) films deposited by pulsed laser deposition method in detail. Except the excellent dielectric properties, including a significant increase in dielectric constant as high as 27.2, a negative flatband voltage of −0.46 V, and a very small loop hysteresis, the YSH film has also shown an obvious response to magnetic field. The saturation magnetization of about 1.3 A m2 kg−1 and 5.8 A m2 kg−1 is presented from the YSH films at 300 K with parallel and perpendicular magnetic field, respectively, which is 20% and 9% larger than that of pure HfO2 film at corresponding magnetic field. It is an indicative approach to control the dielectric properties of hafnium-based oxide films with electric and/or magnetic operation.

Alternative techniques to reduce interface traps in n‐type 4H‐SiC MOS capacitors

AbstractSeveral alternative oxidation techniques are developed and tested with the aim to reduce the high density of interface traps Dit in n‐type 4H‐SiC MOS capacitors. A lamp furnace in combination with a microwave plasma is employed to grow thin oxide layers, which are used for an insulating stack (SiO2 and Al2O3). The treatment of the oxide with nitrogen is another way to lower Dit. We introduce N atoms prior to the oxidation by ion implantation. During the oxidation process, the implanted N‐profile is redistributed; a considerable amount of the implanted N is accumulated at the SiC/SiO2‐interface, which leads to a strong reduction of Dit and a large negative flatband voltage. The negative flatband voltage can largely be compensated by coimplantation of aluminum. A model is proposed, which explains the passivation of interface traps in n‐type 4H‐SiC MOS capacitors. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Electrical Properties and Operating Mechanisms of Nonvolatile Organic Memory Devices Fabricated Utilizing Hybrid Poly(N-vinylcarbazole) and C60 Composites

Organic memory devices based on hybrid poly(N-vinylcarbazole) (PVK) and C60 composites were fabricated with a spin-coating method. Atomic force microscopy images showed that the surface of the PVK layer containing the C60 molecules was relatively smooth. Capacitance–voltage (C–V) measurements on the Al/C60 embedded in PVK layer/p-Si(100) device at room temperature showed a clockwise hysteresis with a large flatband voltage shift due to the existence of the C60 molecules in the PVK layer, indicative of charge storage in the embedded C60 molecules. The clockwise direction of the C–V hysteresis for the devices was attributed to carrier tunneling through the PVK layer emitting from the Al gate electrode, and the negative and positive flatband voltage shifts of the C–V curves originated from the holes and electrons captured in the C60 molecules, respectively. Possible operating mechanisms corresponding to writing and erasing processes for the Al/C60 embedded in PVK layer/p-Si (100) device are described on the basis of the C–V results.

High temperature stability of Hf-based gate dielectric stacks with rare-earth oxide layers for threshold voltage control

The thermal stability of DyOx∕HfSiON and HoOx∕HfSiON gate dielectric stacks on silicon was studied by scanning transmission electron microscopy techniques and correlated with their electrical characteristics. Intermixing of the rare-earth elements with the HfSiON was observed, but there was no diffusion into the interfacial SiO2. Rapid thermal annealing (1000°C) produced little detectable change in the concentration profile of the rare-earth elements but caused thinning of the interfacial SiO2 layer along with a corresponding increase in the rare-earth oxide layer thickness. These reactions could be explained with oxygen deficiency in the rare-earth oxide layer and its greater thermodynamic stability relative to SiO2. Negative flat band voltage shifts were observed relative to a control sample with no DyOx or HoOx. Mechanisms by which the observed microstructure changes could give rise to negative flatband voltage shifts are discussed.

Metal carbide-induced negative flatband voltage shift in TaC x and HfC x/HfO 2 gate stacks

We systematically investigated the role of the top interface for TaC x and HfC x /HfO 2 gate stacks on the effective work function ( Φ m,eff) shift by inserting a SiN layer at the gate/HfO 2 top interface or HfO 2/SiO 2 bottom interface. We found that Φ m,eff of the TaN gate electrode on HfO 2 was larger than that on SiO 2 because of the HfO 2/SiO 2-bottom-interface dipole. On the other hand, we found that Φ m,eff values of the TaC x and HfC x gate electrodes on HfO 2 agree with Φ m,eff on SiO 2. This is because the potential offset of the opposite direction with respect to the bottom interface dipole appears at the metal carbide/HfO 2 interface. It is thus concluded that the top interface in the metal carbide/HfO 2 gate stacks causes the negative Φ m,eff shift.

Control of the Flatband Voltage of 4H-SiC Metal-Oxide Semiconductor (MOS) Capacitors by Co-Implantation of Nitrogen and Aluminum

In n-type 4H-SiC, over-oxidation of an implanted surface-near, Gaussian nitrogen-profile results in MOS capacitors, which possess a distinctly reduced density of interface states Dit and an undesirable large negative flatband voltage UFB. Their values are determined by the implantation parameters and the thickness of the oxide layer. The negative flatband voltage can strongly be compensated in the case that a Gaussian aluminum-profile is co-implanted prior to the oxidation. Depending on the conditions of the Al implantation, UFB can be controlled within a wide range. Secondary ion mass spectrometry analyses reveal that the implanted N and Al atoms are mobile in the oxide layer during the oxidation process and are partly accumulated at the SiC/SiO2 interface.

Study of electrical properties of oxidized porous silicon for back surface passivation of silicon solar cells

Back surface passivation becomes a key issue for the silicon solar cells made with thin wafers. The high surface recombination due to the metal contacts can be lowered by reducing the back contact area and forming local back surface field (LBSF) in conjunction with the passivation with dielectric layer. About 3 × 10 - 7 m thick porous silicon (PS) layer with pore diameter mostly of 1 × 10 - 8 – 5 × 10 - 8 m was formed by chemical etching of silicon using the acidic solution containing hydrofluoric acid (HF), nitric acid (HNO 3) and De-ionized water in the volume ratio 1:3:5 at 298 K for which etching time was kept constant for 360 s. Electrical properties of oxidized PS was studied through the current–voltage ( I – V ) and capacitance–voltage ( C – V ) characteristics of the metal–insulator–semiconductor (MIS) device in which the oxidized PS was used as an insulating layer and the results were further analyzed. The C – V curves of all the studies MIS devices showed the negative flatband voltage varying from - 2 to - 5 V , confirming that the oxidized layer of PS has fixed positive charge.

Electrical properties of germanium/metal-oxide gate stacks with atomic layer deposition grown hafnium-dioxide and plasma-synthesized interface layers

The electrical properties of metal-oxide-semiconductor (MOS) capacitors composed of atomic-layer-deposited (ALD) hafnium-dioxide (HfO2) dielectrics and plasma-synthesized interface layers were investigated. MOS capacitor with oxynitride interface layer shows negative flatband voltage (Vfb) shift from the ideal value. Hafnium-alkylamide ALD process performed on a plasma nitrided silicon surface causes negative Vfb shift. Germanium MOS capacitors show additional negative Vfb shift (−0.5V). X-ray photoelectron spectroscopy shows evidence of germanium diffusion into the HfO2 layer. Germanium MOS capacitor with tantalum-oxynitride (TaON) interface layer shows superior electrical properties. These results indicate that the selection of the interface layer strongly influences germanium MOS capacitor electrical properties.

Electrical characteristics of Si nanocrystal distributed in a narrow layer in the gate oxide near the gate synthesized with very-low-energy ion beams

A nanocrystal Si (nc-Si) distributed in a narrow layer in the gate oxide close to the gate is synthesized with Si ion implantation at 2keV, and the electrical characteristics of the nc-Si structure are investigated. The onset voltage of the Fowler-Nordheim tunneling of the structure is lower than that of pure SiO2 structure, and it decreases with the nc-Si concentration. The phenomenon is attributed to the reduction of the effective thickness of the tunneling oxide. The application of a positive or negative voltage causes electron or hole trapping in the nc-Si, leading to a positive or negative flatband voltage shift, respectively. A steplike flatband voltage shift as a function of charging voltage is observed, suggesting single electron or hole trapping in the nc-Si at room temperature. On the other hand, the nc-Si structure shows good charge-retention characteristics also.

An electrical study of behaviors of Si nanocrystals distributed in the gate oxide near the oxide/substrate interface of a MOS structure

In this work, we have investigated the capacitance–voltage ( C– V) and conductance–voltage ( G– V) characteristics of silicon nanocrystals (nc-Si) distributed in the gate oxide very near the SiO 2/Si interface of a Metal-Oxide-Semiconductor (MOS) structure. The MOS structure is found to be sensitive to only the positive voltage stress from which charging of the nanocrystals causes a negative flatband voltage shift. At the same time, a large conductance peak is observed due to the energy loss via the neutral-nanocrystal paths near the SiO 2/Si interface. Besides, breakdown of the dielectric film containing the nc-Si is also observed from the G– V characteristic.